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d761004bfd
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182047 91177308-0d34-0410-b5e6-96231b3b80d8
70 lines
3.6 KiB
TableGen
70 lines
3.6 KiB
TableGen
let isCodeGenOnly = 1 in {
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/// Arithmetic Instructions (ALU Immediate)
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def ADDiu_MM : MMRel, ArithLogicI<"addiu", simm16, CPURegsOpnd>,
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ADDI_FM_MM<0xc>;
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def ADDi_MM : MMRel, ArithLogicI<"addi", simm16, CPURegsOpnd>,
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ADDI_FM_MM<0x4>;
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def SLTi_MM : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, CPURegs>,
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SLTI_FM_MM<0x24>;
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def SLTiu_MM : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, CPURegs>,
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SLTI_FM_MM<0x2c>;
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def ANDi_MM : MMRel, ArithLogicI<"andi", uimm16, CPURegsOpnd, immZExt16,
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and>,
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ADDI_FM_MM<0x34>;
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def ORi_MM : MMRel, ArithLogicI<"ori", uimm16, CPURegsOpnd, immZExt16, or>,
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ADDI_FM_MM<0x14>;
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def XORi_MM : MMRel, ArithLogicI<"xori", uimm16, CPURegsOpnd, immZExt16,
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xor>,
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ADDI_FM_MM<0x1c>;
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def LUi_MM : MMRel, LoadUpper<"lui", CPURegs, uimm16>, LUI_FM_MM;
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/// Arithmetic Instructions (3-Operand, R-Type)
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def ADDu_MM : MMRel, ArithLogicR<"addu", CPURegsOpnd>, ADD_FM_MM<0, 0x150>;
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def SUBu_MM : MMRel, ArithLogicR<"subu", CPURegsOpnd>, ADD_FM_MM<0, 0x1d0>;
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def MUL_MM : MMRel, ArithLogicR<"mul", CPURegsOpnd>, ADD_FM_MM<0, 0x210>;
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def ADD_MM : MMRel, ArithLogicR<"add", CPURegsOpnd>, ADD_FM_MM<0, 0x110>;
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def SUB_MM : MMRel, ArithLogicR<"sub", CPURegsOpnd>, ADD_FM_MM<0, 0x190>;
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def SLT_MM : MMRel, SetCC_R<"slt", setlt, CPURegs>, ADD_FM_MM<0, 0x350>;
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def SLTu_MM : MMRel, SetCC_R<"sltu", setult, CPURegs>,
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ADD_FM_MM<0, 0x390>;
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def AND_MM : MMRel, ArithLogicR<"and", CPURegsOpnd, 1, IIAlu, and>,
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ADD_FM_MM<0, 0x250>;
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def OR_MM : MMRel, ArithLogicR<"or", CPURegsOpnd, 1, IIAlu, or>,
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ADD_FM_MM<0, 0x290>;
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def XOR_MM : MMRel, ArithLogicR<"xor", CPURegsOpnd, 1, IIAlu, xor>,
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ADD_FM_MM<0, 0x310>;
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def NOR_MM : MMRel, LogicNOR<"nor", CPURegsOpnd>, ADD_FM_MM<0, 0x2d0>;
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def MULT_MM : MMRel, Mult<"mult", IIImul, CPURegsOpnd, [HI, LO]>,
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MULT_FM_MM<0x22c>;
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def MULTu_MM : MMRel, Mult<"multu", IIImul, CPURegsOpnd, [HI, LO]>,
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MULT_FM_MM<0x26c>;
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/// Shift Instructions
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def SLL_MM : MMRel, shift_rotate_imm<"sll", shamt, CPURegsOpnd>,
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SRA_FM_MM<0, 0>;
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def SRL_MM : MMRel, shift_rotate_imm<"srl", shamt, CPURegsOpnd>,
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SRA_FM_MM<0x40, 0>;
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def SRA_MM : MMRel, shift_rotate_imm<"sra", shamt, CPURegsOpnd>,
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SRA_FM_MM<0x80, 0>;
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def SLLV_MM : MMRel, shift_rotate_reg<"sllv", CPURegsOpnd>,
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SRLV_FM_MM<0x10, 0>;
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def SRLV_MM : MMRel, shift_rotate_reg<"srlv", CPURegsOpnd>,
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SRLV_FM_MM<0x50, 0>;
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def SRAV_MM : MMRel, shift_rotate_reg<"srav", CPURegsOpnd>,
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SRLV_FM_MM<0x90, 0>;
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def ROTR_MM : MMRel, shift_rotate_imm<"rotr", shamt, CPURegsOpnd>,
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SRA_FM_MM<0xc0, 0>;
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def ROTRV_MM : MMRel, shift_rotate_reg<"rotrv", CPURegsOpnd>,
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SRLV_FM_MM<0xd0, 0>;
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/// Load and Store Instructions - aligned
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defm LB_MM : LoadM<"lb", CPURegs, sextloadi8>, MMRel, LW_FM_MM<0x7>;
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defm LBu_MM : LoadM<"lbu", CPURegs, zextloadi8>, MMRel, LW_FM_MM<0x5>;
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defm LH_MM : LoadM<"lh", CPURegs, sextloadi16>, MMRel, LW_FM_MM<0xf>;
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defm LHu_MM : LoadM<"lhu", CPURegs, zextloadi16>, MMRel, LW_FM_MM<0xd>;
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defm LW_MM : LoadM<"lw", CPURegs>, MMRel, LW_FM_MM<0x3f>;
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defm SB_MM : StoreM<"sb", CPURegs, truncstorei8>, MMRel, LW_FM_MM<0x6>;
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defm SH_MM : StoreM<"sh", CPURegs, truncstorei16>, MMRel, LW_FM_MM<0xe>;
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defm SW_MM : StoreM<"sw", CPURegs>, MMRel, LW_FM_MM<0x3e>;
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}
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