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acb1111440
Support all instructions with VOP1 encoding with 32 or 64-bit operands for VI subtarget: VGPR_32 and VReg_64 operand register classes VS_32 and VS_64 operand register classes with inline and literal constants Tests for VOP1 instructions. Patch by: skolton Reviewers: arsenm, tstellarAMD Review: http://reviews.llvm.org/D17194 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261878 91177308-0d34-0410-b5e6-96231b3b80d8
460 lines
16 KiB
C++
460 lines
16 KiB
C++
//===-- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA --------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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///
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/// This file contains definition for AMDGPU ISA disassembler
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//
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//===----------------------------------------------------------------------===//
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// ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)?
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#include "AMDGPUDisassembler.h"
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#include "AMDGPU.h"
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#include "AMDGPURegisterInfo.h"
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#include "Utils/AMDGPUBaseInfo.h"
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#include "llvm/MC/MCFixedLenDisassembler.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrDesc.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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#define DEBUG_TYPE "amdgpu-disassembler"
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typedef llvm::MCDisassembler::DecodeStatus DecodeStatus;
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static DecodeStatus DecodeVGPR_32RegisterClass(MCInst &Inst, unsigned Imm,
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uint64_t Addr, const void *Decoder) {
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const AMDGPUDisassembler *Dis =
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static_cast<const AMDGPUDisassembler *>(Decoder);
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return Dis->DecodeVGPR_32RegisterClass(Inst, Imm, Addr);
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}
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static DecodeStatus DecodeVS_32RegisterClass(MCInst &Inst, unsigned Imm,
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uint64_t Addr, const void *Decoder) {
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const AMDGPUDisassembler *Dis =
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static_cast<const AMDGPUDisassembler *>(Decoder);
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return Dis->DecodeVS_32RegisterClass(Inst, Imm, Addr);
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}
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static DecodeStatus DecodeVS_64RegisterClass(MCInst &Inst, unsigned Imm,
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uint64_t Addr, const void *Decoder) {
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const AMDGPUDisassembler *Dis =
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static_cast<const AMDGPUDisassembler *>(Decoder);
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return Dis->DecodeVS_64RegisterClass(Inst, Imm, Addr);
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}
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static DecodeStatus DecodeVReg_64RegisterClass(MCInst &Inst, unsigned Imm,
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uint64_t Addr, const void *Decoder) {
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const AMDGPUDisassembler *Dis =
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static_cast<const AMDGPUDisassembler *>(Decoder);
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return Dis->DecodeVReg_64RegisterClass(Inst, Imm, Addr);
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}
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static DecodeStatus DecodeVReg_96RegisterClass(MCInst &Inst, unsigned Imm,
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uint64_t Addr, const void *Decoder) {
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// ToDo
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return MCDisassembler::Fail;
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}
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static DecodeStatus DecodeVReg_128RegisterClass(MCInst &Inst, unsigned Imm,
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uint64_t Addr, const void *Decoder) {
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// ToDo
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return MCDisassembler::Fail;
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}
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static DecodeStatus DecodeSReg_32RegisterClass(MCInst &Inst, unsigned Imm,
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uint64_t Addr, const void *Decoder) {
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// ToDo
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return MCDisassembler::Fail;
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}
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static DecodeStatus DecodeSReg_64RegisterClass(MCInst &Inst, unsigned Imm,
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uint64_t Addr, const void *Decoder) {
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// ToDo
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return MCDisassembler::Fail;
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}
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static DecodeStatus DecodeSReg_128RegisterClass(MCInst &Inst, unsigned Imm,
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uint64_t Addr, const void *Decoder) {
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// ToDo
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return MCDisassembler::Fail;
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}
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static DecodeStatus DecodeSReg_256RegisterClass(MCInst &Inst, unsigned Imm,
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uint64_t Addr, const void *Decoder) {
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// ToDo
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return MCDisassembler::Fail;
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}
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#define GET_SUBTARGETINFO_ENUM
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#include "AMDGPUGenSubtargetInfo.inc"
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#undef GET_SUBTARGETINFO_ENUM
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#include "AMDGPUGenDisassemblerTables.inc"
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//===----------------------------------------------------------------------===//
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//
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//===----------------------------------------------------------------------===//
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DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
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ArrayRef<uint8_t> Bytes,
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uint64_t Address,
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raw_ostream &WS,
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raw_ostream &CS) const {
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CommentStream = &CS;
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// ToDo: AMDGPUDisassembler supports only VI ISA.
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assert(AMDGPU::isVI(STI) && "Can disassemble only VI ISA.");
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HasLiteral = false;
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this->Bytes = Bytes;
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// Try decode 32-bit instruction
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if (Bytes.size() < 4) {
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Size = 0;
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return MCDisassembler::Fail;
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}
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uint32_t Insn =
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(Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
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// Calling the auto-generated decoder function.
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DecodeStatus Result =
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decodeInstruction(DecoderTableVI32, MI, Insn, Address, this, STI);
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if (Result != MCDisassembler::Success) {
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Size = 0;
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return MCDisassembler::Fail;
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}
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if (HasLiteral == true) {
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Size = 8;
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HasLiteral = false;
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} else {
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Size = 4;
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}
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return MCDisassembler::Success;
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}
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DecodeStatus AMDGPUDisassembler::DecodeImmedFloat(unsigned Imm, uint32_t &F) const {
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// ToDo: case 248: 1/(2*PI) - is allowed only on VI
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// ToDo: AMDGPUInstPrinter does not support 1/(2*PI). It consider 1/(2*PI) as
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// literal constant.
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switch(Imm) {
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case 240: F = FloatToBits(0.5f); return MCDisassembler::Success;
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case 241: F = FloatToBits(-0.5f); return MCDisassembler::Success;
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case 242: F = FloatToBits(1.0f); return MCDisassembler::Success;
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case 243: F = FloatToBits(-1.0f); return MCDisassembler::Success;
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case 244: F = FloatToBits(2.0f); return MCDisassembler::Success;
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case 245: F = FloatToBits(-2.0f); return MCDisassembler::Success;
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case 246: F = FloatToBits(4.0f); return MCDisassembler::Success;
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case 247: F = FloatToBits(-4.0f); return MCDisassembler::Success;
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case 248: F = 0x3e22f983; return MCDisassembler::Success; // 1/(2*PI)
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default: return MCDisassembler::Fail;
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}
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}
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DecodeStatus AMDGPUDisassembler::DecodeImmedDouble(unsigned Imm, uint64_t &D) const {
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switch(Imm) {
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case 240: D = DoubleToBits(0.5); return MCDisassembler::Success;
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case 241: D = DoubleToBits(-0.5); return MCDisassembler::Success;
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case 242: D = DoubleToBits(1.0); return MCDisassembler::Success;
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case 243: D = DoubleToBits(-1.0); return MCDisassembler::Success;
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case 244: D = DoubleToBits(2.0); return MCDisassembler::Success;
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case 245: D = DoubleToBits(-2.0); return MCDisassembler::Success;
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case 246: D = DoubleToBits(4.0); return MCDisassembler::Success;
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case 247: D = DoubleToBits(-4.0); return MCDisassembler::Success;
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case 248: D = 0x3fc45f306dc9c882; return MCDisassembler::Success; // 1/(2*PI)
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default: return MCDisassembler::Fail;
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}
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}
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DecodeStatus AMDGPUDisassembler::DecodeImmedInteger(unsigned Imm,
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int64_t &I) const {
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if ((Imm >= 128) && (Imm <= 192)) {
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I = Imm - 128;
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return MCDisassembler::Success;
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} else if ((Imm >= 193) && (Imm <= 208)) {
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I = 192 - Imm;
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return MCDisassembler::Success;
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}
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return MCDisassembler::Fail;
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}
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DecodeStatus AMDGPUDisassembler::DecodeVgprRegister(unsigned Val,
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unsigned &RegID,
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unsigned Size) const {
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if (Val > (256 - Size / 32)) {
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return MCDisassembler::Fail;
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}
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unsigned RegClassID;
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switch (Size) {
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case 32: RegClassID = AMDGPU::VGPR_32RegClassID; break;
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case 64: RegClassID = AMDGPU::VReg_64RegClassID; break;
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case 96: RegClassID = AMDGPU::VReg_96RegClassID; break;
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case 128: RegClassID = AMDGPU::VReg_128RegClassID; break;
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case 256: RegClassID = AMDGPU::VReg_256RegClassID; break;
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case 512: RegClassID = AMDGPU::VReg_512RegClassID; break;
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default:
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return MCDisassembler::Fail;
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}
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RegID = AMDGPUMCRegisterClasses[RegClassID].getRegister(Val);
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return MCDisassembler::Success;
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}
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DecodeStatus AMDGPUDisassembler::DecodeSgprRegister(unsigned Val,
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unsigned &RegID,
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unsigned Size) const {
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// ToDo: SI/CI have 104 SGPRs, VI - 102
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unsigned RegClassID;
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switch (Size) {
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case 32:
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if (Val > 101) {
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return MCDisassembler::Fail;
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}
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RegClassID = AMDGPU::SGPR_32RegClassID;
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break;
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case 64:
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if ((Val % 2 != 0) || (Val > 100)) {
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return MCDisassembler::Fail;
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}
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Val /= 2;
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RegClassID = AMDGPU::SGPR_64RegClassID;
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break;
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case 128:
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// ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in
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// this bundle?
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if ((Val % 4 != 0) || (Val > 96)) {
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return MCDisassembler::Fail;
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}
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Val /= 4;
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RegClassID = AMDGPU::SReg_128RegClassID;
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break;
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case 256:
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// ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in
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// this bundle?
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if ((Val % 4 != 0) || (Val > 92)) {
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return MCDisassembler::Fail;
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}
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Val /= 4;
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RegClassID = AMDGPU::SReg_256RegClassID;
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break;
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case 512:
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// ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in
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// this bundle?
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if ((Val % 4 != 0) || (Val > 84)) {
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return MCDisassembler::Fail;
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}
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Val /= 4;
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RegClassID = AMDGPU::SReg_512RegClassID;
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break;
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default:
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return MCDisassembler::Fail;
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}
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RegID = AMDGPUMCRegisterClasses[RegClassID].getRegister(Val);
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return MCDisassembler::Success;
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}
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DecodeStatus AMDGPUDisassembler::DecodeSrc32Register(unsigned Val,
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unsigned &RegID) const {
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// ToDo: deal with out-of range registers
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using namespace AMDGPU;
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if (Val <= 101) {
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return DecodeSgprRegister(Val, RegID, 32);
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} else if ((Val >= 256) && (Val <= 511)) {
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return DecodeVgprRegister(Val - 256, RegID, 32);
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} else {
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switch(Val) {
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case 102: RegID = getMCReg(FLAT_SCR_LO, STI); return MCDisassembler::Success;
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case 103: RegID = getMCReg(FLAT_SCR_HI, STI); return MCDisassembler::Success;
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// ToDo: no support for xnack_mask_lo/_hi register
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case 104:
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case 105: return MCDisassembler::Fail;
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case 106: RegID = getMCReg(VCC_LO, STI); return MCDisassembler::Success;
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case 107: RegID = getMCReg(VCC_HI, STI); return MCDisassembler::Success;
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// ToDo: no support for tba_lo/_hi register
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case 108:
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case 109: return MCDisassembler::Fail;
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// ToDo: no support for tma_lo/_hi register
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case 110:
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case 111: return MCDisassembler::Fail;
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// ToDo: no support for ttmp[0:11] register
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case 112:
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case 113:
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case 114:
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case 115:
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case 116:
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case 117:
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case 118:
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case 119:
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case 120:
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case 121:
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case 122:
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case 123: return MCDisassembler::Fail;
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case 124: RegID = getMCReg(M0, STI); return MCDisassembler::Success;
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case 126: RegID = getMCReg(EXEC_LO, STI); return MCDisassembler::Success;
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case 127: RegID = getMCReg(EXEC_HI, STI); return MCDisassembler::Success;
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// ToDo: no support for vccz register
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case 251: return MCDisassembler::Fail;
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// ToDo: no support for execz register
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case 252: return MCDisassembler::Fail;
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case 253: RegID = getMCReg(SCC, STI); return MCDisassembler::Success;
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default: return MCDisassembler::Fail;
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}
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}
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return MCDisassembler::Fail;
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}
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DecodeStatus AMDGPUDisassembler::DecodeSrc64Register(unsigned Val,
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unsigned &RegID) const {
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// ToDo: deal with out-of range registers
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using namespace AMDGPU;
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if (Val <= 101) {
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return DecodeSgprRegister(Val, RegID, 64);
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} else if ((Val >= 256) && (Val <= 511)) {
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return DecodeVgprRegister(Val - 256, RegID, 64);
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} else {
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switch(Val) {
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case 102: RegID = getMCReg(FLAT_SCR, STI); return MCDisassembler::Success;
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case 106: RegID = getMCReg(VCC, STI); return MCDisassembler::Success;
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case 126: RegID = getMCReg(EXEC, STI); return MCDisassembler::Success;
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default: return MCDisassembler::Fail;
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}
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}
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return MCDisassembler::Fail;
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}
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DecodeStatus AMDGPUDisassembler::DecodeLiteralConstant(MCInst &Inst,
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uint64_t &Literal) const {
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// For now all literal constants are supposed to be unsigned integer
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// ToDo: deal with signed/unsigned 64-bit integer constants
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// ToDo: deal with float/double constants
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if (Bytes.size() < 8) {
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return MCDisassembler::Fail;
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}
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Literal =
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0 | (Bytes[7] << 24) | (Bytes[6] << 16) | (Bytes[5] << 8) | (Bytes[4] << 0);
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return MCDisassembler::Success;
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}
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DecodeStatus AMDGPUDisassembler::DecodeVGPR_32RegisterClass(llvm::MCInst &Inst,
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unsigned Imm,
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uint64_t Addr) const {
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unsigned RegID;
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if (DecodeVgprRegister(Imm, RegID) == MCDisassembler::Success) {
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Inst.addOperand(MCOperand::createReg(RegID));
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return MCDisassembler::Success;
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}
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return MCDisassembler::Fail;
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}
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DecodeStatus AMDGPUDisassembler::DecodeVSRegisterClass(MCInst &Inst,
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unsigned Imm,
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uint64_t Addr,
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bool Is32) const {
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// ToDo: different opcodes allow different formats of this operands
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if ((Imm >= 128) && (Imm <= 208)) {
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// immediate integer
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int64_t Val;
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if (DecodeImmedInteger(Imm, Val) == MCDisassembler::Success) {
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Inst.addOperand(MCOperand::createImm(Val));
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return MCDisassembler::Success;
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}
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} else if ((Imm >= 240) && (Imm <= 248)) {
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// immediate float/double
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uint64_t Val;
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DecodeStatus status;
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if (Is32) {
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uint32_t Val32;
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status = DecodeImmedFloat(Imm, Val32);
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Val = static_cast<uint64_t>(Val32);
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} else {
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status = DecodeImmedDouble(Imm, Val);
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}
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if (status == MCDisassembler::Success) {
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Inst.addOperand(MCOperand::createImm(Val));
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return MCDisassembler::Success;
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}
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} else if (Imm == 254) {
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// LDS direct
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// ToDo: implement LDS direct read
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} else if (Imm == 255) {
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// literal constant
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HasLiteral = true;
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uint64_t Literal;
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if (DecodeLiteralConstant(Inst, Literal) == MCDisassembler::Success) {
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Inst.addOperand(MCOperand::createImm(Literal));
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return MCDisassembler::Success;
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}
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return MCDisassembler::Fail;
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} else if ((Imm == 125) ||
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((Imm >= 209) && (Imm <= 239)) ||
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(Imm == 249) ||
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(Imm == 250) ||
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(Imm >= 512)) {
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// reserved
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return MCDisassembler::Fail;
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} else {
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// register
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unsigned RegID;
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DecodeStatus status = Is32 ? DecodeSrc32Register(Imm, RegID)
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: DecodeSrc64Register(Imm, RegID);
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if (status == MCDisassembler::Success) {
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Inst.addOperand(MCOperand::createReg(RegID));
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return MCDisassembler::Success;
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}
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}
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return MCDisassembler::Fail;
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}
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DecodeStatus AMDGPUDisassembler::DecodeVS_32RegisterClass(MCInst &Inst,
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unsigned Imm,
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uint64_t Addr) const {
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return DecodeVSRegisterClass(Inst, Imm, Addr, true);
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}
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DecodeStatus AMDGPUDisassembler::DecodeVS_64RegisterClass(MCInst &Inst,
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unsigned Imm,
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uint64_t Addr) const {
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return DecodeVSRegisterClass(Inst, Imm, Addr, false);
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}
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DecodeStatus AMDGPUDisassembler::DecodeVReg_64RegisterClass(llvm::MCInst &Inst,
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unsigned Imm,
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uint64_t Addr) const {
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unsigned RegID;
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if (DecodeVgprRegister(Imm, RegID, 64) == MCDisassembler::Success) {
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Inst.addOperand(MCOperand::createReg(RegID));
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return MCDisassembler::Success;
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}
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return MCDisassembler::Fail;
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}
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static MCDisassembler *createAMDGPUDisassembler(const Target &T,
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const MCSubtargetInfo &STI,
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MCContext &Ctx) {
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return new AMDGPUDisassembler(STI, Ctx);
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}
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extern "C" void LLVMInitializeAMDGPUDisassembler() {
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TargetRegistry::RegisterMCDisassembler(TheGCNTarget, createAMDGPUDisassembler);
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}
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