Sasa Stankovic f8b83e39c5 [mips] Fix two patterns that select i32's (for MIPS32r6) / i64's (for MIPS64r6) ...

from setne comparison with an i32.

The patterns that are fixed:
  * (select (i32 (setne i32, immZExt16)), i32, i32) (for MIPS32r6)
  * (select (i32 (setne i32, immZExt16)), i64, i64) (for MIPS64r6)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213653 91177308-0d34-0410-b5e6-96231b3b80d8

2014-07-22 13:36:02 +00:00

..

AArch64

CodeGen: emit IR-level f16 conversion intrinsics as fptrunc/fpext

2014-07-21 09:13:56 +00:00

ARM

Replace the result usages while legalizing cmpxchg.

2014-07-21 17:33:44 +00:00

CPP

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Generic

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Hexagon

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Inputs

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Mips

[mips] Fix two patterns that select i32's (for MIPS32r6) / i64's (for MIPS64r6)

2014-07-22 13:36:02 +00:00

MSP430

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NVPTX

Add some tests for NVPTX lowering of cmpxchg

2014-07-21 22:54:44 +00:00

PowerPC

[PowerPC] ELFv2 aggregate passing support

2014-07-21 00:13:26 +00:00

R600

R600/SI: Add instruction shrinking pass

2014-07-21 16:55:33 +00:00

SPARC

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SystemZ

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Thumb

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Thumb2

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X86

AVX-512: Fixed intrinsic of VSQRTPS/PD instructions.

2014-07-22 11:07:31 +00:00

XCore

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