mirror of
https://github.com/RPCS3/llvm.git
synced 2025-05-19 11:55:55 +00:00
ae5fb65ace
This patch extends the MCSchedModel API with new methods that can be used to obtain the latency and reciprocal througput information for an MCInst. Scheduling models have recently gained the ability to resolve variant scheduling classes associated with MCInst objects. Before, models were only able to resolve a variant scheduling class from a MachineInstr object. This patch is mainly required by D47374 to avoid regressing a pair of x86 specific -print-schedule tests for btver2. Patch D47374 introduces a new variant class to teach the btver scheduling model (x86 target) how to correctly compute the latency profile for some zero-idioms using the new scheduling predicates. The new methods added by this patch would be mainly used by llc when flag -print-schedule is specified. In particular, tests that contain inline assembly require that code is parsed at code emission stage into a sequence of MCInst. That forces the print-schedule functionality to query the latency/rthroughput information for MCInst instructions too. If we don't expose this new API, then we lose "-print-schedule" test coverage as soon as variant scheduling classes are added to the x86 models. The tablegen SubtargetEmitter changes teaches how to query latency profile information using a object that derives from TargetSubtargetInfo. Note that this should really have been part of r333286. To avoid code duplication, the logic that "resolves" variant scheduling classes for MCInst, has been moved to a common place in MC. That logic is used by the "resolveVariantSchedClass" methods redefined in override by the tablegen'd GenSubtargetInfo classes. Differential Revision: https://reviews.llvm.org/D47536 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333650 91177308-0d34-0410-b5e6-96231b3b80d8
119 lines
3.8 KiB
C++
119 lines
3.8 KiB
C++
//===- TargetSubtargetInfo.cpp - General Target Information ----------------==//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
/// \file This file describes the general parts of a Subtarget.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#include "llvm/CodeGen/TargetSubtargetInfo.h"
|
|
#include "llvm/ADT/Optional.h"
|
|
#include "llvm/CodeGen/MachineInstr.h"
|
|
#include "llvm/CodeGen/TargetInstrInfo.h"
|
|
#include "llvm/CodeGen/TargetSchedule.h"
|
|
#include "llvm/MC/MCInst.h"
|
|
#include "llvm/Support/Format.h"
|
|
#include "llvm/Support/raw_ostream.h"
|
|
#include <string>
|
|
|
|
using namespace llvm;
|
|
|
|
TargetSubtargetInfo::TargetSubtargetInfo(
|
|
const Triple &TT, StringRef CPU, StringRef FS,
|
|
ArrayRef<SubtargetFeatureKV> PF, ArrayRef<SubtargetFeatureKV> PD,
|
|
const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR,
|
|
const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA,
|
|
const InstrStage *IS, const unsigned *OC, const unsigned *FP)
|
|
: MCSubtargetInfo(TT, CPU, FS, PF, PD, ProcSched, WPR, WL, RA, IS, OC, FP) {
|
|
}
|
|
|
|
TargetSubtargetInfo::~TargetSubtargetInfo() = default;
|
|
|
|
bool TargetSubtargetInfo::enableAtomicExpand() const {
|
|
return true;
|
|
}
|
|
|
|
bool TargetSubtargetInfo::enableIndirectBrExpand() const {
|
|
return false;
|
|
}
|
|
|
|
bool TargetSubtargetInfo::enableMachineScheduler() const {
|
|
return false;
|
|
}
|
|
|
|
bool TargetSubtargetInfo::enableJoinGlobalCopies() const {
|
|
return enableMachineScheduler();
|
|
}
|
|
|
|
bool TargetSubtargetInfo::enableRALocalReassignment(
|
|
CodeGenOpt::Level OptLevel) const {
|
|
return true;
|
|
}
|
|
|
|
bool TargetSubtargetInfo::enableAdvancedRASplitCost() const {
|
|
return false;
|
|
}
|
|
|
|
bool TargetSubtargetInfo::enablePostRAScheduler() const {
|
|
return getSchedModel().PostRAScheduler;
|
|
}
|
|
|
|
bool TargetSubtargetInfo::useAA() const {
|
|
return false;
|
|
}
|
|
|
|
static std::string createSchedInfoStr(unsigned Latency,
|
|
Optional<double> RThroughput) {
|
|
static const char *SchedPrefix = " sched: [";
|
|
std::string Comment;
|
|
raw_string_ostream CS(Comment);
|
|
if (RThroughput.hasValue())
|
|
CS << SchedPrefix << Latency << format(":%2.2f", RThroughput.getValue())
|
|
<< "]";
|
|
else
|
|
CS << SchedPrefix << Latency << ":?]";
|
|
CS.flush();
|
|
return Comment;
|
|
}
|
|
|
|
/// Returns string representation of scheduler comment
|
|
std::string TargetSubtargetInfo::getSchedInfoStr(const MachineInstr &MI) const {
|
|
if (MI.isPseudo() || MI.isTerminator())
|
|
return std::string();
|
|
// We don't cache TSchedModel because it depends on TargetInstrInfo
|
|
// that could be changed during the compilation
|
|
TargetSchedModel TSchedModel;
|
|
TSchedModel.init(this);
|
|
unsigned Latency = TSchedModel.computeInstrLatency(&MI);
|
|
Optional<double> RThroughput = TSchedModel.computeReciprocalThroughput(&MI);
|
|
return createSchedInfoStr(Latency, RThroughput);
|
|
}
|
|
|
|
/// Returns string representation of scheduler comment
|
|
std::string TargetSubtargetInfo::getSchedInfoStr(MCInst const &MCI) const {
|
|
// We don't cache TSchedModel because it depends on TargetInstrInfo
|
|
// that could be changed during the compilation
|
|
TargetSchedModel TSchedModel;
|
|
TSchedModel.init(this);
|
|
unsigned Latency;
|
|
if (TSchedModel.hasInstrSchedModel())
|
|
Latency = TSchedModel.computeInstrLatency(MCI);
|
|
else if (TSchedModel.hasInstrItineraries()) {
|
|
auto *ItinData = TSchedModel.getInstrItineraries();
|
|
Latency = ItinData->getStageLatency(
|
|
getInstrInfo()->get(MCI.getOpcode()).getSchedClass());
|
|
} else
|
|
return std::string();
|
|
Optional<double> RThroughput =
|
|
TSchedModel.computeReciprocalThroughput(MCI);
|
|
return createSchedInfoStr(Latency, RThroughput);
|
|
}
|
|
|
|
void TargetSubtargetInfo::mirFileLoaded(MachineFunction &MF) const {
|
|
}
|