Simon Atanasyan dab9d81b7c [mips] Fix local dynamic TLS with Sym64 ...

For the final DTPREL addition, rather than a lui/daddiu/daddu triple,
LLVM was erronously emitting a daddiu/daddiu pair, treating the %dtprel_hi
as if it were a %dtprel_lo, since Mips::Hi expands unshifted for Sym64.
Instead, use a new TlsHi node and, although unnecessary due to the exact
structure of the nodes emitted, use TlsHi for local exec too to prevent
future bugs. Also garbage-collect the unused TprelLo and TlsGd nodes,
and TprelHi since its functionality is provided by the new common TlsHi node.

Patch by James Clarke.

Differential revision: https://reviews.llvm.org/D49259

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337827 91177308-0d34-0410-b5e6-96231b3b80d8

2018-07-24 13:47:52 +00:00

..

AArch64

[AArch64] Use MCAsmInfoMicrosoft and MCAsmInfoGNUCOFF as base classes

2018-07-23 22:15:14 +00:00

AMDGPU

AMDGPU/GlobalISel: Legalize G_INSERT

2018-07-24 02:19:20 +00:00

ARC

[ARC] Add ARC backend.

2017-08-24 15:40:33 +00:00

ARM

[ARM] Disable ARMCodeGenPrepare by default

2018-07-24 12:04:23 +00:00

AVR

[AVR] Set trackLivenessAfterRegAlloc

2018-06-11 14:46:48 +00:00

BPF

[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.

2018-05-09 02:40:45 +00:00

Generic

Implement strip.invariant.group

2018-07-02 04:49:30 +00:00

Hexagon

[Hexagon] Handle unnamed globals in HexagonConstExpr

2018-07-23 18:30:17 +00:00

Inputs

…

Lanai

Remove SETCCE use from Lanai's backend

2018-06-03 12:56:24 +00:00

Mips

[mips] Fix local dynamic TLS with Sym64

2018-07-24 13:47:52 +00:00

MIR

[DebugInfo][X86] Add start-after flags to MIR tests

2018-07-12 14:36:48 +00:00

MSP430

Emit a left-shift instead of a power-of-two multiply for jump-tables

2018-05-16 08:58:26 +00:00

Nios2

[Nios2] Arithmetic instructions for R1 and R2 ISA.

2018-01-09 11:15:08 +00:00

NVPTX

finish: [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests

2018-07-11 20:31:51 +00:00

PowerPC

[Power9] Code Cleanup - Remove needsAggressiveScheduling()

2018-07-19 19:34:18 +00:00

RISCV

[RISCV] Add machine function pass to merge base + offset

2018-06-27 20:51:42 +00:00

SPARC

Regenerate remainder test.

2018-07-20 13:14:29 +00:00

SystemZ

[SystemZ] Test case formatting fixes

2018-07-20 12:12:10 +00:00

Thumb

[CodeGen] Emit more precise AssertZext/AssertSext nodes.

2018-07-11 23:26:35 +00:00

Thumb2

[ARM] Treat cmn immediates as legal in isLegalICmpImmediate.

2018-07-10 23:44:37 +00:00

WebAssembly

[WebAssembly] Add missing -mattr=+exception-handling guards

2018-07-18 21:42:22 +00:00

WinCFGuard

Reland "Emit Function IDs table for Control Flow Guard"

2018-01-09 23:49:30 +00:00

WinEH

[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.

2018-05-09 02:40:45 +00:00

X86

[x86] Clean up and convert test to use generated CHECK lines.

2018-07-24 03:18:08 +00:00

XCore

[DAGCombiner] extend(ifpositive(X)) -> shift-right (not X)

2018-07-15 16:27:07 +00:00