mirror of
https://github.com/RPCS3/llvm.git
synced 2026-07-22 11:45:31 -04:00
Jonas Paulsson
78f5683a63
The SchedModel allows the addition of ReadAdvances to express that certain operands of the instructions are needed at a later point than the others. RegAlloc may add pseudo operands that are not part of the instruction descriptor, and therefore cannot have any read advance entries. This meant that in some cases the desired read advance was nullified by such a pseudo operand, which still had the original latency. This patch fixes this by making sure that such pseudo operands get a zero latency during DAG construction. Review: Matthias Braun, Ulrich Weigand. https://reviews.llvm.org/D49671 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345606 91177308-0d34-0410-b5e6-96231b3b80d8
145 lines
3.9 KiB
LLVM
145 lines
3.9 KiB
LLVM
; RUN: llc -mtriple=arm-apple-darwin %s -o - | FileCheck %s
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; RUN: llc -mtriple=arm-eabi -mattr=+vfp2 %s -o - \
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; RUN: | FileCheck %s --check-prefix=CHECK-VFP
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; RUN: llc -mtriple=thumbv7-apple-darwin -mattr=+neon,+thumb2 %s -o - \
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; RUN: | FileCheck %s --check-prefix=CHECK-NEON
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define i32 @f1(i32 %a.s) {
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;CHECK-LABEL: f1:
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;CHECK: moveq
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entry:
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%tmp = icmp eq i32 %a.s, 4
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%tmp1.s = select i1 %tmp, i32 2, i32 3
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ret i32 %tmp1.s
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}
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define i32 @f2(i32 %a.s) {
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;CHECK-LABEL: f2:
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;CHECK: movgt
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entry:
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%tmp = icmp sgt i32 %a.s, 4
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%tmp1.s = select i1 %tmp, i32 2, i32 3
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ret i32 %tmp1.s
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}
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define i32 @f3(i32 %a.s, i32 %b.s) {
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;CHECK-LABEL: f3:
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;CHECK: movlt
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entry:
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%tmp = icmp slt i32 %a.s, %b.s
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%tmp1.s = select i1 %tmp, i32 2, i32 3
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ret i32 %tmp1.s
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}
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define i32 @f4(i32 %a.s, i32 %b.s) {
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;CHECK-LABEL: f4:
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;CHECK: movle
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entry:
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%tmp = icmp sle i32 %a.s, %b.s
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%tmp1.s = select i1 %tmp, i32 2, i32 3
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ret i32 %tmp1.s
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}
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define i32 @f5(i32 %a.u, i32 %b.u) {
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;CHECK-LABEL: f5:
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;CHECK: movls
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entry:
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%tmp = icmp ule i32 %a.u, %b.u
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%tmp1.s = select i1 %tmp, i32 2, i32 3
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ret i32 %tmp1.s
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}
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define i32 @f6(i32 %a.u, i32 %b.u) {
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;CHECK-LABEL: f6:
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;CHECK: movhi
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entry:
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%tmp = icmp ugt i32 %a.u, %b.u
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%tmp1.s = select i1 %tmp, i32 2, i32 3
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ret i32 %tmp1.s
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}
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define double @f7(double %a, double %b) {
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;CHECK-LABEL: f7:
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;CHECK: movlt
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;CHECK: movge
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;CHECK-VFP-LABEL: f7:
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;CHECK-VFP: vmovmi
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%tmp = fcmp olt double %a, 1.234e+00
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%tmp1 = select i1 %tmp, double -1.000e+00, double %b
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ret double %tmp1
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}
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; <rdar://problem/7260094>
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;
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; We used to generate really horrible code for this function. The main cause was
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; a lack of a custom lowering routine for an ISD::SELECT. This would result in
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; two "it" blocks in the code: one for the "icmp" and another to move the index
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; into the constant pool based on the value of the "icmp". If we have one "it"
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; block generated, odds are good that we have close to the ideal code for this:
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;
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; CHECK-NEON-LABEL: f8:
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; CHECK-NEON: adr [[R2:r[0-9]+]], LCPI7_0
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; CHECK-NEON: movw [[R3:r[0-9]+]], #1123
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; CHECK-NEON-NEXT: cmp r0, [[R3]]
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; CHECK-NEON-NEXT: it eq
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; CHECK-NEON-NEXT: addeq{{.*}} [[R2]], #4
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; CHECK-NEON-NEXT: ldr
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; CHECK-NEON: bx
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define arm_apcscc float @f8(i32 %a) nounwind {
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%tmp = icmp eq i32 %a, 1123
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%tmp1 = select i1 %tmp, float 0x3FF3BE76C0000000, float 0x40030E9A20000000
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ret float %tmp1
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}
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; <rdar://problem/9049552>
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; Glue values can only have a single use, but the following test exposed a
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; case where a SELECT was lowered with 2 uses of a comparison, causing the
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; scheduler to assert.
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; CHECK-VFP-LABEL: f9:
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declare i8* @objc_msgSend(i8*, i8*, ...)
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define void @f9() optsize {
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entry:
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%cmp = icmp eq i8* undef, inttoptr (i32 4 to i8*)
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%conv191 = select i1 %cmp, float -3.000000e+00, float 0.000000e+00
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%conv195 = select i1 %cmp, double -1.000000e+00, double 0.000000e+00
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%add = fadd double %conv195, 1.100000e+01
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%conv196 = fptrunc double %add to float
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%add201 = fadd float undef, %conv191
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%tmp484 = bitcast float %conv196 to i32
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%tmp478 = bitcast float %add201 to i32
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%tmp490 = insertvalue [2 x i32] undef, i32 %tmp484, 0
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%tmp493 = insertvalue [2 x i32] %tmp490, i32 %tmp478, 1
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call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*, [2 x i32], i32, float)*)(i8* undef, i8* undef, [2 x i32] %tmp493, i32 0, float 1.000000e+00) optsize
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ret void
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}
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; CHECK-LABEL: f10:
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define float @f10(i32 %a, i32 %b) nounwind uwtable readnone ssp {
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; CHECK-NOT: floatsisf
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%1 = icmp eq i32 %a, %b
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%2 = zext i1 %1 to i32
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%3 = sitofp i32 %2 to float
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ret float %3
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}
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; CHECK-LABEL: f11:
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define float @f11(i32 %a, i32 %b) nounwind uwtable readnone ssp {
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; CHECK-NOT: floatsisf
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%1 = icmp eq i32 %a, %b
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%2 = sitofp i1 %1 to float
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ret float %2
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}
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; CHECK-LABEL: f12:
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define float @f12(i32 %a, i32 %b) nounwind uwtable readnone ssp {
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; CHECK-NOT: floatunsisf
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%1 = icmp eq i32 %a, %b
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%2 = uitofp i1 %1 to float
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ret float %2
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}
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