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a TargetMachine to construct (and thus isn't always available), to an analysis group that supports layered implementations much like AliasAnalysis does. This is a pretty massive change, with a few parts that I was unable to easily separate (sorry), so I'll walk through it. The first step of this conversion was to make TargetTransformInfo an analysis group, and to sink the nonce implementations in ScalarTargetTransformInfo and VectorTargetTranformInfo into a NoTargetTransformInfo pass. This allows other passes to add a hard requirement on TTI, and assume they will always get at least on implementation. The TargetTransformInfo analysis group leverages the delegation chaining trick that AliasAnalysis uses, where the base class for the analysis group delegates to the previous analysis *pass*, allowing all but tho NoFoo analysis passes to only implement the parts of the interfaces they support. It also introduces a new trick where each pass in the group retains a pointer to the top-most pass that has been initialized. This allows passes to implement one API in terms of another API and benefit when some other pass above them in the stack has more precise results for the second API. The second step of this conversion is to create a pass that implements the TargetTransformInfo analysis using the target-independent abstractions in the code generator. This replaces the ScalarTargetTransformImpl and VectorTargetTransformImpl classes in lib/Target with a single pass in lib/CodeGen called BasicTargetTransformInfo. This class actually provides most of the TTI functionality, basing it upon the TargetLowering abstraction and other information in the target independent code generator. The third step of the conversion adds support to all TargetMachines to register custom analysis passes. This allows building those passes with access to TargetLowering or other target-specific classes, and it also allows each target to customize the set of analysis passes desired in the pass manager. The baseline LLVMTargetMachine implements this interface to add the BasicTTI pass to the pass manager, and all of the tools that want to support target-aware TTI passes call this routine on whatever target machine they end up with to add the appropriate passes. The fourth step of the conversion created target-specific TTI analysis passes for the X86 and ARM backends. These passes contain the custom logic that was previously in their extensions of the ScalarTargetTransformInfo and VectorTargetTransformInfo interfaces. I separated them into their own file, as now all of the interface bits are private and they just expose a function to create the pass itself. Then I extended these target machines to set up a custom set of analysis passes, first adding BasicTTI as a fallback, and then adding their customized TTI implementations. The fourth step required logic that was shared between the target independent layer and the specific targets to move to a different interface, as they no longer derive from each other. As a consequence, a helper functions were added to TargetLowering representing the common logic needed both in the target implementation and the codegen implementation of the TTI pass. While technically this is the only change that could have been committed separately, it would have been a nightmare to extract. The final step of the conversion was just to delete all the old boilerplate. This got rid of the ScalarTargetTransformInfo and VectorTargetTransformInfo classes, all of the support in all of the targets for producing instances of them, and all of the support in the tools for manually constructing a pass based around them. Now that TTI is a relatively normal analysis group, two things become straightforward. First, we can sink it into lib/Analysis which is a more natural layer for it to live. Second, clients of this interface can depend on it *always* being available which will simplify their code and behavior. These (and other) simplifications will follow in subsequent commits, this one is clearly big enough. Finally, I'm very aware that much of the comments and documentation needs to be updated. As soon as I had this working, and plausibly well commented, I wanted to get it committed and in front of the build bots. I'll be doing a few passes over documentation later if it sticks. Commits to update DragonEgg and Clang will be made presently. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171681 91177308-0d34-0410-b5e6-96231b3b80d8 |
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| .. | ||
| InstPrinter | ||
| MCTargetDesc | ||
| TargetInfo | ||
| CMakeLists.txt | ||
| LLVMBuild.txt | ||
| Makefile | ||
| MSP430.h | ||
| MSP430.td | ||
| MSP430AsmPrinter.cpp | ||
| MSP430BranchSelector.cpp | ||
| MSP430CallingConv.td | ||
| MSP430FrameLowering.cpp | ||
| MSP430FrameLowering.h | ||
| MSP430InstrFormats.td | ||
| MSP430InstrInfo.cpp | ||
| MSP430InstrInfo.h | ||
| MSP430InstrInfo.td | ||
| MSP430ISelDAGToDAG.cpp | ||
| MSP430ISelLowering.cpp | ||
| MSP430ISelLowering.h | ||
| MSP430MachineFunctionInfo.cpp | ||
| MSP430MachineFunctionInfo.h | ||
| MSP430MCInstLower.cpp | ||
| MSP430MCInstLower.h | ||
| MSP430RegisterInfo.cpp | ||
| MSP430RegisterInfo.h | ||
| MSP430RegisterInfo.td | ||
| MSP430SelectionDAGInfo.cpp | ||
| MSP430SelectionDAGInfo.h | ||
| MSP430Subtarget.cpp | ||
| MSP430Subtarget.h | ||
| MSP430TargetMachine.cpp | ||
| MSP430TargetMachine.h | ||
| README.txt | ||
//===---------------------------------------------------------------------===// // MSP430 backend. //===---------------------------------------------------------------------===// DISCLAIMER: Thid backend should be considered as highly experimental. I never seen nor worked with this MCU, all information was gathered from datasheet only. The original intention of making this backend was to write documentation of form "How to write backend for dummies" :) Thes notes hopefully will be available pretty soon. Some things are incomplete / not implemented yet (this list surely is not complete as well): 1. Verify, how stuff is handling implicit zext with 8 bit operands (this might be modelled currently in improper way - should we need to mark the superreg as def for every 8 bit instruction?). 2. Libcalls: multiplication, division, remainder. Note, that calling convention for libcalls is incomptible with calling convention of libcalls of msp430-gcc (these cannot be used though due to license restriction). 3. Implement multiplication / division by constant (dag combiner hook?). 4. Implement non-constant shifts. 5. Implement varargs stuff. 6. Verify and fix (if needed) how's stuff playing with i32 / i64. 7. Implement floating point stuff (softfp?) 8. Implement instruction encoding for (possible) direct code emission in the future. 9. Since almost all instructions set flags - implement brcond / select in better way (currently they emit explicit comparison). 10. Handle imm in comparisons in better way (see comment in MSP430InstrInfo.td) 11. Implement hooks for better memory op folding, etc.