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llvm/test/CodeGen
Craig Topper af156f2d96 [AVX-512] Remove patterns that select vmovdqu8/16 for unmasked loads. Prefer vmovdqa64/vmovdqu64 instead.
These were taking priority over the aligned load instructions since there is no vmovda8/16. I don't think there is really a difference between aligned and unaligned on newer cpus so I don't think it matters which instructions we use.

But with this change we reduce the size of the isel table a little and we allow the aligned information to pass through to the evex->vec pass and produce the same output has avx/avx2 in some cases.

I also generally dislike patterns rooted in a bitcast which these were.

Differential Revision: https://reviews.llvm.org/D35977

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309589 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-31 17:35:44 +00:00
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