Craig Topper 46cba73063 [X86] When using AND+PACKUS in lowerV16I8Shuffle, generate the build vector directly in v16i8 with the correct 0x00 or 0xFF elements rather than using another VT and bitcasting it. ...

The build_vector will become a constant pool load. By using the
desired type initially, it ensures we don't generate a bitcast
of the constant pool load which will need to be folded with
the load.

While experimenting with another patch, I noticed that when the
load type and the constant pool type don't match, then
SimplifyDemandedBits can't handle it. While we should probably
fix that, this was a simple way to fix the issue I saw.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366732 91177308-0d34-0410-b5e6-96231b3b80d8

2019-07-22 19:58:49 +00:00

..

AArch64

[GISel]: Attach missing range metadata while translating G_LOADs

2019-07-21 14:07:54 +00:00

AMDGPU

[AMDGPU] Test update. NFC.

2019-07-22 18:08:53 +00:00

ARC

[lit] Delete empty lines at the end of lit.local.cfg NFC

2019-06-17 09:51:07 +00:00

ARM

[IPRA][ARM] Make use of the "returned" parameter attribute

2019-07-22 08:44:36 +00:00

AVR

[AVR] Fix tests after r363757

2019-07-04 06:12:47 +00:00

BPF

[BPF] add unit tests for preserve_{array,union,struct}_access_index intrinsics

2019-07-15 04:51:34 +00:00

Generic

Revert "r364412 [ExpandMemCmp][MergeICmps] Move passes out of CodeGen into opt pipeline."

2019-06-26 12:13:13 +00:00

Hexagon

[Hexagon] Custom-lower UADDO(x, 1) and USUBO(x, 1)

2019-07-01 15:50:09 +00:00

Inputs

[CodeGen] Add stack protector tests where the guard gets re-assigned

2019-07-17 20:46:16 +00:00

Lanai

[SDAG] commute setcc operands to match a subtract

2019-07-10 23:23:54 +00:00

Mips

[GlobalISel] Translate calls to memcpy et al to G_INTRINSIC_W_SIDE_EFFECTs and legalize later.

2019-07-19 00:24:45 +00:00

MIR

[PowerPC][NFC] Precommit a test case where ppc-mi-peepholes miscompiles extswsli

2019-07-22 05:32:20 +00:00

MSP430

[lit] Delete empty lines at the end of lit.local.cfg NFC

2019-06-17 09:51:07 +00:00

NVPTX

[NVPTX] Use atomicrmw fadd instead of intrinsics

2019-07-11 17:11:25 +00:00

PowerPC

[NFC][PowerPC]Change ADDIStocHA to ADDIStocHA8 to follow 64-bit naming convention

2019-07-22 19:55:33 +00:00

RISCV

[DebugInfo] Generate fixups as emitting DWARF .debug_frame/.eh_frame.

2019-07-19 02:03:34 +00:00

SPARC

[lit] Delete empty lines at the end of lit.local.cfg NFC

2019-06-17 09:51:07 +00:00

SystemZ

[Strict FP] Allow more relaxed scheduling

2019-07-16 15:55:45 +00:00

Thumb

[ARM] Favour PL/MI over GE/LT when possible

2019-07-04 08:58:58 +00:00

Thumb2

[ARM][LowOverheadLoops] Revert remaining pseudos

2019-07-22 14:16:40 +00:00

WebAssembly

[WebAssembly] Compute and export TLS block alignment

2019-07-19 23:34:16 +00:00

WinCFGuard

[COFF] Emit @feat.00 on 64-bit and set the CFG bit when emitting guardcf tables

2018-09-19 09:58:30 +00:00

WinEH

[lit] Delete empty lines at the end of lit.local.cfg NFC

2019-06-17 09:51:07 +00:00

X86

[X86] When using AND+PACKUS in lowerV16I8Shuffle, generate the build vector directly in v16i8 with the correct 0x00 or 0xFF elements rather than using another VT and bitcasting it.

2019-07-22 19:58:49 +00:00

XCore

[lit] Delete empty lines at the end of lit.local.cfg NFC

2019-06-17 09:51:07 +00:00