Sam Parker b0917b06be [ARM] Fix for DLS/LE CodeGen ...

The expensive buildbots highlighted the mir tests were broken, which
I've now updated and added --verify-machineinstrs to them. This also
uncovered a couple of bugs in the backend pass, so these have also
been fixed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364323 91177308-0d34-0410-b5e6-96231b3b80d8

2019-06-25 15:11:17 +00:00

..

ARM

[ARM] Fix for DLS/LE CodeGen

2019-06-25 15:11:17 +00:00

scalar-while.ll

[CodeGen] Generic Hardware Loop Support

2019-06-07 07:35:30 +00:00

unconditional-latch.ll

[CodeGen] Check for HardwareLoop Latch ExitBlock

2019-06-17 13:39:28 +00:00

unscevable.ll

[CodeGen] Generic Hardware Loop Support

2019-06-07 07:35:30 +00:00