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b1e8cad61e
which is represented in codegen as an 'and' operation. This matches them with movz instructions, instead of leaving them to be matched by and instructions with an immediate field. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54147 91177308-0d34-0410-b5e6-96231b3b80d8
63 lines
1.5 KiB
LLVM
63 lines
1.5 KiB
LLVM
; RUN: llvm-as < %s | llc -march=x86 | not grep and
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; RUN: llvm-as < %s | llc -march=x86-64 | not grep and
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; These should use movzbl instead of 'and 255'.
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; This related to not having a ZERO_EXTEND_REG opcode.
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define i32 @a(i32 %d) nounwind {
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%e = add i32 %d, 1
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%retval = and i32 %e, 255
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ret i32 %retval
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}
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define i32 @b(float %d) nounwind {
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%tmp12 = fptoui float %d to i8
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%retval = zext i8 %tmp12 to i32
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ret i32 %retval
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}
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define i32 @c(i32 %d) nounwind {
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%e = add i32 %d, 1
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%retval = and i32 %e, 65535
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ret i32 %retval
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}
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define i64 @d(i64 %d) nounwind {
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%e = add i64 %d, 1
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%retval = and i64 %e, 255
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ret i64 %retval
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}
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define i64 @e(i64 %d) nounwind {
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%e = add i64 %d, 1
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%retval = and i64 %e, 65535
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ret i64 %retval
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}
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define i64 @f(i64 %d) nounwind {
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%e = add i64 %d, 1
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%retval = and i64 %e, 4294967295
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ret i64 %retval
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}
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define i32 @g(i8 %d) nounwind {
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%e = add i8 %d, 1
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%retval = zext i8 %e to i32
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ret i32 %retval
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}
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define i32 @h(i16 %d) nounwind {
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%e = add i16 %d, 1
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%retval = zext i16 %e to i32
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ret i32 %retval
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}
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define i64 @i(i8 %d) nounwind {
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%e = add i8 %d, 1
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%retval = zext i8 %e to i64
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ret i64 %retval
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}
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define i64 @j(i16 %d) nounwind {
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%e = add i16 %d, 1
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%retval = zext i16 %e to i64
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ret i64 %retval
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}
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define i64 @k(i32 %d) nounwind {
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%e = add i32 %d, 1
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%retval = zext i32 %e to i64
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ret i64 %retval
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}
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