Duncan Sands b2df01ab2a Codegen support for arbitrary vector getelementptrs. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167830 91177308-0d34-0410-b5e6-96231b3b80d8		2012-11-13 13:01:58 +00:00
..
ARM	Cleanup the main RegisterCoalescer loop.	2012-11-13 00:34:44 +00:00
CellSPU	Fix broken tests.	2012-10-02 15:49:34 +00:00
CPP	test commit	2012-07-18 17:53:05 +00:00
Generic	Codegen support for arbitrary vector getelementptrs.	2012-11-13 13:01:58 +00:00
Hexagon	LLVM Bug Fix 13709: Remove needless lsr(Rp, #32) instruction access the	2012-09-05 16:01:40 +00:00
MBlaze	Continue cleanup of LIT, getting rid of the remaining artifacts from dejagnu	2012-03-25 09:02:19 +00:00
Mips	[mips] Custom-lower ISD::FRAME_TO_ARGS_OFFSET node.	2012-11-07 19:10:58 +00:00
MSP430	Fix fallout from RegInfo => FrameLowering refactoring on MSP430.	2012-10-17 17:37:11 +00:00
NVPTX	[NVPTX] Add more precise PTX/SM target attributes	2012-11-12 03:16:43 +00:00
PowerPC	Fix assertions in updateRegMaskSlots().	2012-11-09 19:18:49 +00:00
SPARC	Use TargetTransformInfo to control switch-to-lookup table transformation	2012-10-30 11:23:25 +00:00
Thumb	Convert an improper CodeGen test to a MC test.	2012-11-10 04:30:40 +00:00
Thumb2	Add GPRPair Register class to ARM.	2012-10-26 21:29:15 +00:00
X86	Use the 'count' attribute instead of the 'upper_bound' attribute.	2012-11-13 02:31:47 +00:00
XCore	Fix pattern for MKMSK instruction.	2012-06-13 17:59:12 +00:00