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e3a9b4ce3a
All these headers already depend on CodeGen headers so moving them into CodeGen fixes the layering (since CodeGen depends on Target, not the other way around). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318490 91177308-0d34-0410-b5e6-96231b3b80d8
81 lines
2.4 KiB
C++
81 lines
2.4 KiB
C++
//===--- ARMComputeBlockSize.cpp - Compute machine block sizes ------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "ARM.h"
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#include "ARMBaseInstrInfo.h"
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#include "ARMBasicBlockInfo.h"
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#include "ARMMachineFunctionInfo.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include <vector>
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using namespace llvm;
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namespace llvm {
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// mayOptimizeThumb2Instruction - Returns true if optimizeThumb2Instructions
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// below may shrink MI.
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static bool
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mayOptimizeThumb2Instruction(const MachineInstr *MI) {
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switch(MI->getOpcode()) {
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// optimizeThumb2Instructions.
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case ARM::t2LEApcrel:
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case ARM::t2LDRpci:
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// optimizeThumb2Branches.
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case ARM::t2B:
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case ARM::t2Bcc:
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case ARM::tBcc:
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// optimizeThumb2JumpTables.
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case ARM::t2BR_JT:
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return true;
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}
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return false;
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}
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void computeBlockSize(MachineFunction *MF, MachineBasicBlock *MBB,
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BasicBlockInfo &BBI) {
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const ARMBaseInstrInfo *TII =
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static_cast<const ARMBaseInstrInfo *>(MF->getSubtarget().getInstrInfo());
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bool isThumb = MF->getInfo<ARMFunctionInfo>()->isThumbFunction();
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BBI.Size = 0;
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BBI.Unalign = 0;
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BBI.PostAlign = 0;
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for (MachineInstr &I : *MBB) {
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BBI.Size += TII->getInstSizeInBytes(I);
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// For inline asm, getInstSizeInBytes returns a conservative estimate.
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// The actual size may be smaller, but still a multiple of the instr size.
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if (I.isInlineAsm())
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BBI.Unalign = isThumb ? 1 : 2;
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// Also consider instructions that may be shrunk later.
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else if (isThumb && mayOptimizeThumb2Instruction(&I))
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BBI.Unalign = 1;
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}
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// tBR_JTr contains a .align 2 directive.
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if (!MBB->empty() && MBB->back().getOpcode() == ARM::tBR_JTr) {
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BBI.PostAlign = 2;
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MBB->getParent()->ensureAlignment(2);
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}
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}
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std::vector<BasicBlockInfo> computeAllBlockSizes(MachineFunction *MF) {
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std::vector<BasicBlockInfo> BBInfo;
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BBInfo.resize(MF->getNumBlockIDs());
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for (MachineBasicBlock &MBB : *MF)
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computeBlockSize(MF, &MBB, BBInfo[MBB.getNumber()]);
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return BBInfo;
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}
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} // end namespace llvm
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