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e3e43d9d57
I did this a long time ago with a janky python script, but now clang-format has built-in support for this. I fed clang-format every line with a #include and let it re-sort things according to the precise LLVM rules for include ordering baked into clang-format these days. I've reverted a number of files where the results of sorting includes isn't healthy. Either places where we have legacy code relying on particular include ordering (where possible, I'll fix these separately) or where we have particular formatting around #include lines that I didn't want to disturb in this patch. This patch is *entirely* mechanical. If you get merge conflicts or anything, just ignore the changes in this patch and run clang-format over your #include lines in the files. Sorry for any noise here, but it is important to keep these things stable. I was seeing an increasing number of patches with irrelevant re-ordering of #include lines because clang-format was used. This patch at least isolates that churn, makes it easy to skip when resolving conflicts, and gets us to a clean baseline (again). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304787 91177308-0d34-0410-b5e6-96231b3b80d8
100 lines
3.3 KiB
C++
100 lines
3.3 KiB
C++
//===-- WebAssemblyReplacePhysRegs.cpp - Replace phys regs with virt regs -===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// \brief This file implements a pass that replaces physical registers with
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/// virtual registers.
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///
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/// LLVM expects certain physical registers, such as a stack pointer. However,
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/// WebAssembly doesn't actually have such physical registers. This pass is run
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/// once LLVM no longer needs these registers, and replaces them with virtual
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/// registers, so they can participate in register stackifying and coloring in
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/// the normal way.
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///
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
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#include "WebAssembly.h"
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#include "WebAssemblyMachineFunctionInfo.h"
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#include "WebAssemblySubtarget.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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#define DEBUG_TYPE "wasm-replace-phys-regs"
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namespace {
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class WebAssemblyReplacePhysRegs final : public MachineFunctionPass {
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public:
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static char ID; // Pass identification, replacement for typeid
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WebAssemblyReplacePhysRegs() : MachineFunctionPass(ID) {}
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private:
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StringRef getPassName() const override {
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return "WebAssembly Replace Physical Registers";
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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};
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} // end anonymous namespace
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char WebAssemblyReplacePhysRegs::ID = 0;
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FunctionPass *llvm::createWebAssemblyReplacePhysRegs() {
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return new WebAssemblyReplacePhysRegs();
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}
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bool WebAssemblyReplacePhysRegs::runOnMachineFunction(MachineFunction &MF) {
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DEBUG({
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dbgs() << "********** Replace Physical Registers **********\n"
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<< "********** Function: " << MF.getName() << '\n';
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});
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MachineRegisterInfo &MRI = MF.getRegInfo();
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const auto &TRI = *MF.getSubtarget<WebAssemblySubtarget>().getRegisterInfo();
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bool Changed = false;
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assert(!mustPreserveAnalysisID(LiveIntervalsID) &&
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"LiveIntervals shouldn't be active yet!");
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// We don't preserve SSA or liveness.
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MRI.leaveSSA();
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MRI.invalidateLiveness();
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for (unsigned PReg = WebAssembly::NoRegister + 1;
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PReg < WebAssembly::NUM_TARGET_REGS; ++PReg) {
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// Skip fake registers that are never used explicitly.
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if (PReg == WebAssembly::VALUE_STACK || PReg == WebAssembly::ARGUMENTS)
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continue;
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// Replace explicit uses of the physical register with a virtual register.
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const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(PReg);
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unsigned VReg = WebAssembly::NoRegister;
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for (auto I = MRI.reg_begin(PReg), E = MRI.reg_end(); I != E; ) {
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MachineOperand &MO = *I++;
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if (!MO.isImplicit()) {
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if (VReg == WebAssembly::NoRegister)
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VReg = MRI.createVirtualRegister(RC);
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MO.setReg(VReg);
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if (MO.getParent()->isDebugValue())
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MO.setIsDebug();
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Changed = true;
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}
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}
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}
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return Changed;
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}
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