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b3325ffee4
This re-commits everything that was pulled in r314244. The transformation is off by default (patch to enable it to follow). The code is refactored to have a single entry-point and provide fine-grained control over patterns that it selects. This patch also fixes the bugs in the original code. Everything that failed with the original patch has been re-tested with this patch (with the transformation turned on). So the patch to turn this on is soon to follow. Differential Revision: https://reviews.llvm.org/D38575 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319434 91177308-0d34-0410-b5e6-96231b3b80d8
138 lines
4.0 KiB
LLVM
138 lines
4.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
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; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
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; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
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; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
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; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
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@glob = common local_unnamed_addr global i8 0, align 1
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; Function Attrs: norecurse nounwind readnone
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define i64 @test_llequc(i8 zeroext %a, i8 zeroext %b) {
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; CHECK-LABEL: test_llequc:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: xor r3, r3, r4
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; CHECK-NEXT: cntlzw r3, r3
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; CHECK-NEXT: srwi r3, r3, 5
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp eq i8 %a, %b
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%conv3 = zext i1 %cmp to i64
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ret i64 %conv3
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}
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; Function Attrs: norecurse nounwind readnone
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define i64 @test_llequc_sext(i8 zeroext %a, i8 zeroext %b) {
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; CHECK-LABEL: test_llequc_sext:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: xor r3, r3, r4
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; CHECK-NEXT: cntlzw r3, r3
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; CHECK-NEXT: srwi r3, r3, 5
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; CHECK-NEXT: neg r3, r3
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp eq i8 %a, %b
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%conv3 = sext i1 %cmp to i64
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ret i64 %conv3
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}
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; Function Attrs: norecurse nounwind readnone
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define i64 @test_llequc_z(i8 zeroext %a) {
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; CHECK-LABEL: test_llequc_z:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: cntlzw r3, r3
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; CHECK-NEXT: srwi r3, r3, 5
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp eq i8 %a, 0
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%conv2 = zext i1 %cmp to i64
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ret i64 %conv2
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}
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; Function Attrs: norecurse nounwind readnone
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define i64 @test_llequc_sext_z(i8 zeroext %a) {
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; CHECK-LABEL: test_llequc_sext_z:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: cntlzw r3, r3
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; CHECK-NEXT: srwi r3, r3, 5
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; CHECK-NEXT: neg r3, r3
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp eq i8 %a, 0
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%conv2 = sext i1 %cmp to i64
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ret i64 %conv2
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}
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; Function Attrs: norecurse nounwind
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define void @test_llequc_store(i8 zeroext %a, i8 zeroext %b) {
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; CHECK-LABEL: test_llequc_store:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
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; CHECK-NEXT: xor r3, r3, r4
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; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
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; CHECK-NEXT: cntlzw r3, r3
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; CHECK-NEXT: srwi r3, r3, 5
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; CHECK-NEXT: stb r3, 0(r12)
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp eq i8 %a, %b
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%conv3 = zext i1 %cmp to i8
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store i8 %conv3, i8* @glob, align 1
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ret void
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}
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; Function Attrs: norecurse nounwind
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define void @test_llequc_sext_store(i8 zeroext %a, i8 zeroext %b) {
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; CHECK-LABEL: test_llequc_sext_store:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: xor r3, r3, r4
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; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
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; CHECK-NEXT: cntlzw r3, r3
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; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
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; CHECK-NEXT: srwi r3, r3, 5
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; CHECK-NEXT: neg r3, r3
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; CHECK-NEXT: stb r3, 0(r4)
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp eq i8 %a, %b
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%conv3 = sext i1 %cmp to i8
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store i8 %conv3, i8* @glob, align 1
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ret void
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}
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; Function Attrs: norecurse nounwind
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define void @test_llequc_z_store(i8 zeroext %a) {
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; CHECK-LABEL: test_llequc_z_store:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
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; CHECK-NEXT: cntlzw r3, r3
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; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
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; CHECK-NEXT: srwi r3, r3, 5
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; CHECK-NEXT: stb r3, 0(r4)
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp eq i8 %a, 0
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%conv2 = zext i1 %cmp to i8
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store i8 %conv2, i8* @glob, align 1
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ret void
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}
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; Function Attrs: norecurse nounwind
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define void @test_llequc_sext_z_store(i8 zeroext %a) {
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; CHECK-LABEL: test_llequc_sext_z_store:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
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; CHECK-NEXT: cntlzw r3, r3
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; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
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; CHECK-NEXT: srwi r3, r3, 5
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; CHECK-NEXT: neg r3, r3
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; CHECK-NEXT: stb r3, 0(r4)
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp eq i8 %a, 0
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%conv2 = sext i1 %cmp to i8
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store i8 %conv2, i8* @glob, align 1
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ret void
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}
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