mirror of
https://github.com/RPCS3/llvm.git
synced 2026-07-21 03:05:26 -04:00
Neil Henning
b461f4de29
This commit adds a new IR level pass to the AMDGPU backend to perform atomic optimizations. It works by: - Running through a function and finding atomicrmw add/sub or uses of the atomic buffer intrinsics for add/sub. - If all arguments except the value to be added/subtracted are uniform, record the value to be optimized. - Run through the atomic operations we can optimize and, depending on whether the value is uniform/divergent use wavefront wide operations (DPP in the divergent case) to calculate the total amount to be atomically added/subtracted. - Then let only a single lane of each wavefront perform the atomic operation, reducing the total number of atomic operations in flight. - Lastly we recombine the result from the single lane to each lane of the wavefront, and calculate our individual lanes offset into the final result. Differential Revision: https://reviews.llvm.org/D51969 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343973 91177308-0d34-0410-b5e6-96231b3b80d8
128 lines
3.9 KiB
CMake
128 lines
3.9 KiB
CMake
set(LLVM_TARGET_DEFINITIONS AMDGPU.td)
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tablegen(LLVM AMDGPUGenAsmMatcher.inc -gen-asm-matcher)
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tablegen(LLVM AMDGPUGenAsmWriter.inc -gen-asm-writer)
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tablegen(LLVM AMDGPUGenCallingConv.inc -gen-callingconv)
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tablegen(LLVM AMDGPUGenDAGISel.inc -gen-dag-isel)
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tablegen(LLVM AMDGPUGenDisassemblerTables.inc -gen-disassembler)
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tablegen(LLVM AMDGPUGenInstrInfo.inc -gen-instr-info)
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tablegen(LLVM AMDGPUGenIntrinsicEnums.inc -gen-tgt-intrinsic-enums)
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tablegen(LLVM AMDGPUGenIntrinsicImpl.inc -gen-tgt-intrinsic-impl)
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tablegen(LLVM AMDGPUGenMCCodeEmitter.inc -gen-emitter)
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tablegen(LLVM AMDGPUGenMCPseudoLowering.inc -gen-pseudo-lowering)
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tablegen(LLVM AMDGPUGenRegisterBank.inc -gen-register-bank)
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tablegen(LLVM AMDGPUGenRegisterInfo.inc -gen-register-info)
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tablegen(LLVM AMDGPUGenSearchableTables.inc -gen-searchable-tables)
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tablegen(LLVM AMDGPUGenSubtargetInfo.inc -gen-subtarget)
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set(LLVM_TARGET_DEFINITIONS AMDGPUGISel.td)
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tablegen(LLVM AMDGPUGenGlobalISel.inc -gen-global-isel)
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set(LLVM_TARGET_DEFINITIONS R600.td)
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tablegen(LLVM R600GenAsmWriter.inc -gen-asm-writer)
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tablegen(LLVM R600GenCallingConv.inc -gen-callingconv)
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tablegen(LLVM R600GenDAGISel.inc -gen-dag-isel)
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tablegen(LLVM R600GenDFAPacketizer.inc -gen-dfa-packetizer)
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tablegen(LLVM R600GenInstrInfo.inc -gen-instr-info)
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tablegen(LLVM R600GenMCCodeEmitter.inc -gen-emitter)
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tablegen(LLVM R600GenRegisterInfo.inc -gen-register-info)
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tablegen(LLVM R600GenSubtargetInfo.inc -gen-subtarget)
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add_public_tablegen_target(AMDGPUCommonTableGen)
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add_llvm_target(AMDGPUCodeGen
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AMDGPUAliasAnalysis.cpp
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AMDGPUAlwaysInlinePass.cpp
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AMDGPUAnnotateKernelFeatures.cpp
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AMDGPUAnnotateUniformValues.cpp
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AMDGPUArgumentUsageInfo.cpp
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AMDGPUAsmPrinter.cpp
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AMDGPUAtomicOptimizer.cpp
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AMDGPUCallLowering.cpp
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AMDGPUCodeGenPrepare.cpp
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AMDGPUFrameLowering.cpp
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AMDGPUHSAMetadataStreamer.cpp
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AMDGPUInstrInfo.cpp
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AMDGPUInstructionSelector.cpp
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AMDGPUIntrinsicInfo.cpp
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AMDGPUISelDAGToDAG.cpp
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AMDGPUISelLowering.cpp
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AMDGPULegalizerInfo.cpp
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AMDGPULibCalls.cpp
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AMDGPULibFunc.cpp
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AMDGPULowerIntrinsics.cpp
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AMDGPULowerKernelArguments.cpp
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AMDGPULowerKernelAttributes.cpp
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AMDGPUMachineCFGStructurizer.cpp
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AMDGPUMachineFunction.cpp
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AMDGPUMachineModuleInfo.cpp
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AMDGPUMacroFusion.cpp
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AMDGPUMCInstLower.cpp
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AMDGPUOpenCLEnqueuedBlockLowering.cpp
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AMDGPUPromoteAlloca.cpp
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AMDGPURegAsmNames.inc.cpp
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AMDGPURegisterBankInfo.cpp
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AMDGPURegisterInfo.cpp
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AMDGPURewriteOutArguments.cpp
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AMDGPUSubtarget.cpp
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AMDGPUTargetMachine.cpp
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AMDGPUTargetObjectFile.cpp
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AMDGPUTargetTransformInfo.cpp
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AMDGPUUnifyDivergentExitNodes.cpp
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AMDGPUUnifyMetadata.cpp
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AMDGPUInline.cpp
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AMDGPUPerfHintAnalysis.cpp
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AMDILCFGStructurizer.cpp
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GCNHazardRecognizer.cpp
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GCNIterativeScheduler.cpp
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GCNMinRegStrategy.cpp
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GCNRegPressure.cpp
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GCNSchedStrategy.cpp
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R600AsmPrinter.cpp
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R600ClauseMergePass.cpp
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R600ControlFlowFinalizer.cpp
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R600EmitClauseMarkers.cpp
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R600ExpandSpecialInstrs.cpp
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R600FrameLowering.cpp
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R600InstrInfo.cpp
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R600ISelLowering.cpp
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R600MachineFunctionInfo.cpp
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R600MachineScheduler.cpp
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R600OpenCLImageTypeLoweringPass.cpp
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R600OptimizeVectorRegisters.cpp
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R600Packetizer.cpp
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R600RegisterInfo.cpp
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SIAnnotateControlFlow.cpp
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SIDebuggerInsertNops.cpp
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SIFixSGPRCopies.cpp
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SIFixVGPRCopies.cpp
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SIFixWWMLiveness.cpp
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SIFoldOperands.cpp
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SIFormMemoryClauses.cpp
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SIFrameLowering.cpp
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SIInsertSkips.cpp
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SIInsertWaitcnts.cpp
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SIInstrInfo.cpp
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SIISelLowering.cpp
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SILoadStoreOptimizer.cpp
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SILowerControlFlow.cpp
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SILowerI1Copies.cpp
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SIMachineFunctionInfo.cpp
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SIMachineScheduler.cpp
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SIMemoryLegalizer.cpp
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SIOptimizeExecMasking.cpp
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SIOptimizeExecMaskingPreRA.cpp
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SIPeepholeSDWA.cpp
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SIRegisterInfo.cpp
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SIShrinkInstructions.cpp
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SIWholeQuadMode.cpp
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GCNILPSched.cpp
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)
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add_subdirectory(AsmParser)
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add_subdirectory(Disassembler)
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add_subdirectory(InstPrinter)
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add_subdirectory(MCTargetDesc)
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add_subdirectory(TargetInfo)
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add_subdirectory(Utils)
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