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This change deals with intrinsics with multiple outputs, for example load instrinsic with address updated. DAG selection for Instrinsics could be done either through source code or tablegen. Handling all intrinsics in source code would introduce a huge chunk of repetitive code if we have a large number of intrinsic that return multiple values (see NVPTX as an example). While intrinsic class in tablegen supports multiple outputs, tablegen only supports Intrinsics with zero or one output on TreePattern. This appears to be a simple bug in tablegen that is fixed by this change. For Intrinsics defined as: def int_xxx_load_addr_updated: Intrinsic<[llvm_i32_ty, llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty], []>; Instruction will be defined as: def L32_X: Inst<(outs reg:$d1, reg:$d2), (ins reg:$s1, reg:$s2), "ld32_x $d1, $d2, $s2", [(set i32:$d1, i32:$d2, (int_xxx_load_addr_updated i32:$s1, i32:$s2))]>; Patch by Wenbo Sun, thanks! Differential Revision: https://reviews.llvm.org/D32888 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321704 91177308-0d34-0410-b5e6-96231b3b80d8
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