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llvm/lib/Target/R600
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Tom Stellard b52bf6a3b3 R600/SI: Prefer SALU instructions for bit shift operations 
All shift operations will be selected as SALU instructions and then
if necessary lowered to VALU instructions in the SIFixSGPRCopies pass.

This allows us to do more operations on the SALU which will improve
performance and is also required for implementing private memory
using indirect addressing, since the private memory pointers must stay
in the scalar registers.

This patch includes some fixes from Matt Arsenault.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194625 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-13 23:36:37 +00:00
..
InstPrinter
R600/SI: Change formatting of printed registers.
2013-11-12 02:35:51 +00:00
MCTargetDesc
Remove AllowQuotesInName and friends from MCAsmInfo.
2013-11-13 14:01:59 +00:00
TargetInfo
R600: Remove unnecessary include
2013-06-07 20:28:43 +00:00
AMDGPU.h
R600: Simplify handling of private address space
2013-10-22 18:19:10 +00:00
AMDGPU.td
R600/SI: Add compute support for CI v2
2013-10-29 16:37:28 +00:00
AMDGPUAsmPrinter.cpp
R600/SI: Add compute support for CI v2
2013-10-29 16:37:28 +00:00
AMDGPUAsmPrinter.h
Fix missing C++ mode comment
2013-11-10 01:03:59 +00:00
AMDGPUCallingConv.td
R600: Use function inputs to represent data stored in gpr
2013-11-11 22:10:24 +00:00
AMDGPUConvertToISA.cpp
…
AMDGPUFrameLowering.cpp
R600: Fix calculation of stack offset in AMDGPUFrameLowering
2013-06-07 20:52:05 +00:00
AMDGPUFrameLowering.h
R600: Support for indirect addressing v4
2013-02-06 17:32:29 +00:00
AMDGPUInstrInfo.cpp
Removing a switch statement that contains only a default label. This resolves an MSVC warning. No functional change intended.
2013-10-29 20:40:52 +00:00
AMDGPUInstrInfo.h
R600: Simplify handling of private address space
2013-10-22 18:19:10 +00:00
AMDGPUInstrInfo.td
R600: Add support for i8 and i16 local memory stores
2013-08-26 15:05:49 +00:00
AMDGPUInstructions.td
Target/R600: Un-tab-ify.
2013-10-28 04:07:23 +00:00
AMDGPUIntrinsics.td
R600: Add support for GROUP_BARRIER instruction
2013-06-28 15:46:59 +00:00
AMDGPUISelDAGToDAG.cpp
ISelDAG: spot chain cycles involving MachineNodes
2013-09-22 08:21:56 +00:00
AMDGPUISelLowering.cpp
R600: Fix LowerUDIVREM
2013-11-06 17:36:04 +00:00
AMDGPUISelLowering.h
R600: Custom lower f32 = uint_to_fp i64
2013-10-30 17:22:05 +00:00
AMDGPUMachineFunction.cpp
Move string pointer from being a static class member to just a static global in the one file its needed in.
2013-07-17 00:31:35 +00:00
AMDGPUMachineFunction.h
R600: Fix incorrect LDS size calculation
2013-09-05 18:37:57 +00:00
AMDGPUMCInstLower.cpp
R600: Store disassembly in a special ELF section when feature +DumpCode is enabled.
2013-10-12 05:02:51 +00:00
AMDGPUMCInstLower.h
R600: BB operand support for SI
2012-12-17 15:14:54 +00:00
AMDGPURegisterInfo.cpp
R600/SI: Lower BUILD_VECTOR to REG_SEQUENCE v2
2013-08-14 23:24:32 +00:00
AMDGPURegisterInfo.h
R600/SI: Lower BUILD_VECTOR to REG_SEQUENCE v2
2013-08-14 23:24:32 +00:00
AMDGPURegisterInfo.td
Make SubRegIndex size mandatory, following r183020.
2013-05-31 23:45:26 +00:00
AMDGPUSubtarget.cpp
R600: Use StructurizeCFGPass for non SI targets
2013-10-10 17:11:12 +00:00
AMDGPUSubtarget.h
R600/SI: Add compute support for CI v2
2013-10-29 16:37:28 +00:00
AMDGPUTargetMachine.cpp
R600: Fix handling of vector kernel arguments
2013-10-23 00:44:32 +00:00
AMDGPUTargetMachine.h
SimplifyCFG: Use parallel-and and parallel-or mode to consolidate branch conditions
2013-07-27 00:01:07 +00:00
AMDGPUTargetTransformInfo.cpp
SimplifyCFG: Use parallel-and and parallel-or mode to consolidate branch conditions
2013-07-27 00:01:07 +00:00
AMDILBase.td
R600: Move Subtarget feature definitions into AMDGPU.td
2013-06-07 20:28:49 +00:00
AMDILCFGStructurizer.cpp
R600: Remove \ at EOL from ascii art comments.
2013-10-18 14:12:50 +00:00
AMDILInstrInfo.td
R600: Enable -verify-machineinstrs in some tests.
2013-10-01 19:32:38 +00:00
AMDILIntrinsicInfo.cpp
R600: Rework subtarget info and remove AMDILDevice classes
2013-06-07 20:37:48 +00:00
AMDILIntrinsicInfo.h
Move all of the header files which are involved in modelling the LLVM IR
2013-01-02 11:36:10 +00:00
AMDILIntrinsics.td
R600/SI: Use MULADD_IEEE/V_MAD_F32 instruction for mad pattern
2013-02-18 14:11:28 +00:00
AMDILISelLowering.cpp
Make some arrays 'static const'
2013-07-15 06:39:13 +00:00
AMDILRegisterInfo.td
…
CMakeLists.txt
R600: Simplify handling of private address space
2013-10-22 18:19:10 +00:00
LLVMBuild.txt
…
Makefile
…
Processors.td
R600/SI: Add compute support for CI v2
2013-10-29 16:37:28 +00:00
R600ClauseMergePass.cpp
R600: add a pass that merges clauses.
2013-10-01 19:32:58 +00:00
R600ControlFlowFinalizer.cpp
R600: Add IsExport bit to TableGen instruction definitions
2013-08-16 01:11:51 +00:00
R600Defines.h
R600: Add support for i8 and i16 local memory stores
2013-08-26 15:05:49 +00:00
R600EmitClauseMarkers.cpp
R600: Use StructurizeCFGPass for non SI targets
2013-10-10 17:11:12 +00:00
R600ExpandSpecialInstrs.cpp
R600: Remove predicated_break inst
2013-07-31 19:31:14 +00:00
R600InstrFormats.td
R600: Use SchedModel enum for is{Trans,Vector}Only functions
2013-09-04 19:53:30 +00:00
R600InstrInfo.cpp
R600: Simplify handling of private address space
2013-10-22 18:19:10 +00:00
R600InstrInfo.h
R600: Simplify handling of private address space
2013-10-22 18:19:10 +00:00
R600Instructions.td
R600: Use function inputs to represent data stored in gpr
2013-11-11 22:10:24 +00:00
R600Intrinsics.td
R600: Reenable llvm.R600.load.input/interp.input for compatibility
2013-11-12 16:26:47 +00:00
R600ISelLowering.cpp
R600: Fix selection failure on EXTLOAD
2013-11-13 02:39:07 +00:00
R600ISelLowering.h
R600: Move fabs/fneg/sel folding logic into PostProcessIsel
2013-09-12 23:44:44 +00:00
R600MachineFunctionInfo.cpp
R600/SI: Share code recording ShaderTypeAttribute between generations
2013-04-01 21:47:53 +00:00
R600MachineFunctionInfo.h
Move passes from namespace llvm into anonymous namespaces. Sort includes while there.
2013-05-23 17:10:37 +00:00
R600MachineScheduler.cpp
R600: Don't use trans slot for instructions that read LDS source registers
2013-09-12 02:55:06 +00:00
R600MachineScheduler.h
R600: Non vector only instruction can be scheduled on trans unit
2013-09-04 19:53:46 +00:00
R600OptimizeVectorRegisters.cpp
R600: Enable folding of inline literals into REQ_SEQUENCE instructions
2013-08-16 01:11:55 +00:00
R600Packetizer.cpp
R600: Simplify handling of private address space
2013-10-22 18:19:10 +00:00
R600RegisterInfo.cpp
R600: Simplify handling of private address space
2013-10-22 18:19:10 +00:00
R600RegisterInfo.h
R600/SI: Lower BUILD_VECTOR to REG_SEQUENCE v2
2013-08-14 23:24:32 +00:00
R600RegisterInfo.td
R600: Simplify handling of private address space
2013-10-22 18:19:10 +00:00
R600Schedule.td
R600: Add local memory support via LDS
2013-06-28 15:47:08 +00:00
R600TextureIntrinsicsReplacer.cpp
R600: Coding style
2013-09-05 23:55:13 +00:00
SIAnnotateControlFlow.cpp
Add 'const' qualifiers to static const char* variables.
2013-07-16 01:17:10 +00:00
SIDefines.h
R600/SI: Prefer SALU instructions for bit shift operations
2013-11-13 23:36:37 +00:00
SIFixSGPRCopies.cpp
R600/SI: Prefer SALU instructions for bit shift operations
2013-11-13 23:36:37 +00:00
SIInsertWaits.cpp
R600/SI: Fix broken encoding of DS_WRITE_B32
2013-08-16 16:19:24 +00:00
SIInstrFormats.td
R600/SI: Prefer SALU instructions for bit shift operations
2013-11-13 23:36:37 +00:00
SIInstrInfo.cpp
R600/SI: Prefer SALU instructions for bit shift operations
2013-11-13 23:36:37 +00:00
SIInstrInfo.h
R600/SI: Prefer SALU instructions for bit shift operations
2013-11-13 23:36:37 +00:00
SIInstrInfo.td
R600/SI: Prefer SALU instructions for bit shift operations
2013-11-13 23:36:37 +00:00
SIInstructions.td
R600/SI: Prefer SALU instructions for bit shift operations
2013-11-13 23:36:37 +00:00
SIIntrinsics.td
R600/SI: expose TBUFFER_STORE_FORMAT_* for OpenGL transform feedback
2013-09-12 02:55:14 +00:00
SIISelLowering.cpp
R600/SI: Replace ffs(x) - 1 with countTrailingZeros(x)
2013-10-23 03:50:25 +00:00
SIISelLowering.h
R600: Fix handling of vector kernel arguments
2013-10-23 00:44:32 +00:00
SILowerControlFlow.cpp
R600: Add support for local memory atomic add
2013-09-05 18:38:09 +00:00
SIMachineFunctionInfo.cpp
R600/SI: Share code recording ShaderTypeAttribute between generations
2013-04-01 21:47:53 +00:00
SIMachineFunctionInfo.h
R600/SI: Share code recording ShaderTypeAttribute between generations
2013-04-01 21:47:53 +00:00
SIRegisterInfo.cpp
R600/SI: Prefer SALU instructions for bit shift operations
2013-11-13 23:36:37 +00:00
SIRegisterInfo.h
R600/SI: Prefer SALU instructions for bit shift operations
2013-11-13 23:36:37 +00:00
SIRegisterInfo.td
R600: Fix handling of vector kernel arguments
2013-10-23 00:44:32 +00:00
SISchedule.td
…
SITypeRewriter.cpp
R600/SI: Replace v1i32 type with i32 in imageload and sample intrinsics
2013-08-14 23:24:53 +00:00