mirror of
https://github.com/RPCS3/llvm.git
synced 2024-12-24 13:06:56 +00:00
c60e76d139
.set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
LPCRELL0:
add r1, pc, #PCRELV0
This is not legal since add r1, pc, #c requires the constant be a multiple of 4.
Do the following instead:
.set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
LPCRELL0:
mov r1, #PCRELV0
add r1, pc
- In thumb mode, it's not possible to use .set generate a pc relative stub
address. The stub is ARM code which is in a different section from the thumb
code. Load the value from a constpool instead.
- Some asm printing clean up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33664 91177308-0d34-0410-b5e6-96231b3b80d8
1150 lines
44 KiB
TableGen
1150 lines
44 KiB
TableGen
//===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the "Instituto Nokia de Tecnologia" and
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// is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the ARM instructions in TableGen format.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// ARM specific DAG Nodes.
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//
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// Type profiles.
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def SDT_ARMCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
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def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
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def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
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def SDT_ARMCMov : SDTypeProfile<1, 3,
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[SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
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SDTCisVT<3, i32>]>;
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def SDT_ARMBrcond : SDTypeProfile<0, 2,
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[SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
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def SDT_ARMBrJT : SDTypeProfile<0, 3,
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[SDTCisPtrTy<0>, SDTCisVT<1, i32>,
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SDTCisVT<2, i32>]>;
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def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
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def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
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SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
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// Node definitions.
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def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
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def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
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def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeq,
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[SDNPHasChain, SDNPOutFlag]>;
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def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeq,
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[SDNPHasChain, SDNPOutFlag]>;
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def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
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[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
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def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
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[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
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def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTRet,
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[SDNPHasChain, SDNPOptInFlag]>;
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def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
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[SDNPInFlag]>;
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def ARMcneg : SDNode<"ARMISD::CNEG", SDT_ARMCMov,
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[SDNPInFlag]>;
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def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
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[SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
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def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
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[SDNPHasChain]>;
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def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
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[SDNPOutFlag]>;
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def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
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def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
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def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
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def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInFlag ]>;
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//===----------------------------------------------------------------------===//
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// ARM Instruction Predicate Definitions.
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//
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def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
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def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">;
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def HasV6 : Predicate<"Subtarget->hasV6Ops()">;
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def IsThumb : Predicate<"Subtarget->isThumb()">;
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def IsARM : Predicate<"!Subtarget->isThumb()">;
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//===----------------------------------------------------------------------===//
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// ARM Flag Definitions.
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class RegConstraint<string C> {
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string Constraints = C;
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}
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//===----------------------------------------------------------------------===//
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// ARM specific transformation functions and pattern fragments.
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//
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// so_imm_XFORM - Return a so_imm value packed into the format described for
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// so_imm def below.
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def so_imm_XFORM : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(N->getValue()),
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MVT::i32);
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}]>;
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// so_imm_neg_XFORM - Return a so_imm value packed into the format described for
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// so_imm_neg def below.
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def so_imm_neg_XFORM : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(-(int)N->getValue()),
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MVT::i32);
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}]>;
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// so_imm_not_XFORM - Return a so_imm value packed into the format described for
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// so_imm_not def below.
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def so_imm_not_XFORM : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(~(int)N->getValue()),
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MVT::i32);
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}]>;
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// rot_imm predicate - True if the 32-bit immediate is equal to 8, 16, or 24.
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def rot_imm : PatLeaf<(i32 imm), [{
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int32_t v = (int32_t)N->getValue();
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return v == 8 || v == 16 || v == 24;
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}]>;
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/// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
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def imm1_15 : PatLeaf<(i32 imm), [{
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return (int32_t)N->getValue() >= 1 && (int32_t)N->getValue() < 16;
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}]>;
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/// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
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def imm16_31 : PatLeaf<(i32 imm), [{
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return (int32_t)N->getValue() >= 16 && (int32_t)N->getValue() < 32;
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}]>;
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def so_imm_neg :
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PatLeaf<(imm), [{ return ARM_AM::getSOImmVal(-(int)N->getValue()) != -1; }],
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so_imm_neg_XFORM>;
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def so_imm_not :
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PatLeaf<(imm), [{ return ARM_AM::getSOImmVal(~(int)N->getValue()) != -1; }],
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so_imm_not_XFORM>;
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// sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
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def sext_16_node : PatLeaf<(i32 GPR:$a), [{
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return TLI.ComputeNumSignBits(SDOperand(N,0)) >= 17;
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}]>;
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// Break so_imm's up into two pieces. This handles immediates with up to 16
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// bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
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// get the first/second pieces.
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def so_imm2part : PatLeaf<(imm), [{
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return ARM_AM::isSOImmTwoPartVal((unsigned)N->getValue());
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}]>;
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def so_imm2part_1 : SDNodeXForm<imm, [{
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unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getValue());
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return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(V), MVT::i32);
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}]>;
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def so_imm2part_2 : SDNodeXForm<imm, [{
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unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getValue());
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return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(V), MVT::i32);
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}]>;
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//===----------------------------------------------------------------------===//
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// Operand Definitions.
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//
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// Branch target.
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def brtarget : Operand<OtherVT>;
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// Operand for printing out a condition code.
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def CCOp : Operand<i32> {
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let PrintMethod = "printCCOperand";
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}
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// A list of registers separated by comma. Used by load/store multiple.
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def reglist : Operand<i32> {
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let PrintMethod = "printRegisterList";
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}
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// An operand for the CONSTPOOL_ENTRY pseudo-instruction.
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def cpinst_operand : Operand<i32> {
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let PrintMethod = "printCPInstOperand";
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}
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def jtblock_operand : Operand<i32> {
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let PrintMethod = "printJTBlockOperand";
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}
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// Local PC labels.
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def pclabel : Operand<i32> {
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let PrintMethod = "printPCLabel";
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}
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// shifter_operand operands: so_reg and so_imm.
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def so_reg : Operand<i32>, // reg reg imm
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ComplexPattern<i32, 3, "SelectShifterOperandReg",
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[shl,srl,sra,rotr]> {
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let PrintMethod = "printSORegOperand";
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let MIOperandInfo = (ops GPR, GPR, i32imm);
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}
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// so_imm - Match a 32-bit shifter_operand immediate operand, which is an
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// 8-bit immediate rotated by an arbitrary number of bits. so_imm values are
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// represented in the imm field in the same 12-bit form that they are encoded
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// into so_imm instructions: the 8-bit immediate is the least significant bits
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// [bits 0-7], the 4-bit shift amount is the next 4 bits [bits 8-11].
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def so_imm : Operand<i32>,
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PatLeaf<(imm),
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[{ return ARM_AM::getSOImmVal(N->getValue()) != -1; }],
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so_imm_XFORM> {
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let PrintMethod = "printSOImmOperand";
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}
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// Define ARM specific addressing modes.
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// addrmode2 := reg +/- reg shop imm
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// addrmode2 := reg +/- imm12
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//
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def addrmode2 : Operand<i32>,
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ComplexPattern<i32, 3, "SelectAddrMode2", []> {
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let PrintMethod = "printAddrMode2Operand";
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let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
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}
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def am2offset : Operand<i32>,
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ComplexPattern<i32, 2, "SelectAddrMode2Offset", []> {
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let PrintMethod = "printAddrMode2OffsetOperand";
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let MIOperandInfo = (ops GPR, i32imm);
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}
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// addrmode3 := reg +/- reg
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// addrmode3 := reg +/- imm8
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//
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def addrmode3 : Operand<i32>,
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ComplexPattern<i32, 3, "SelectAddrMode3", []> {
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let PrintMethod = "printAddrMode3Operand";
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let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
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}
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def am3offset : Operand<i32>,
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ComplexPattern<i32, 2, "SelectAddrMode3Offset", []> {
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let PrintMethod = "printAddrMode3OffsetOperand";
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let MIOperandInfo = (ops GPR, i32imm);
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}
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// addrmode4 := reg, <mode|W>
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//
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def addrmode4 : Operand<i32>,
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ComplexPattern<i32, 2, "", []> {
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let PrintMethod = "printAddrMode4Operand";
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let MIOperandInfo = (ops GPR, i32imm);
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}
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// addrmode5 := reg +/- imm8*4
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//
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def addrmode5 : Operand<i32>,
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ComplexPattern<i32, 2, "SelectAddrMode5", []> {
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let PrintMethod = "printAddrMode5Operand";
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let MIOperandInfo = (ops GPR, i32imm);
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}
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// addrmodepc := pc + reg
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//
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def addrmodepc : Operand<i32>,
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ComplexPattern<i32, 2, "SelectAddrModePC", []> {
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let PrintMethod = "printAddrModePCOperand";
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let MIOperandInfo = (ops GPR, i32imm);
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}
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//===----------------------------------------------------------------------===//
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// ARM Instruction flags. These need to match ARMInstrInfo.h.
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//
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// Addressing mode.
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class AddrMode<bits<4> val> {
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bits<4> Value = val;
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}
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def AddrModeNone : AddrMode<0>;
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def AddrMode1 : AddrMode<1>;
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def AddrMode2 : AddrMode<2>;
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def AddrMode3 : AddrMode<3>;
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def AddrMode4 : AddrMode<4>;
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def AddrMode5 : AddrMode<5>;
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def AddrModeT1 : AddrMode<6>;
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def AddrModeT2 : AddrMode<7>;
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def AddrModeT4 : AddrMode<8>;
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def AddrModeTs : AddrMode<9>;
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// Instruction size.
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class SizeFlagVal<bits<3> val> {
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bits<3> Value = val;
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}
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def SizeInvalid : SizeFlagVal<0>; // Unset.
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def SizeSpecial : SizeFlagVal<1>; // Pseudo or special.
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def Size8Bytes : SizeFlagVal<2>;
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def Size4Bytes : SizeFlagVal<3>;
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def Size2Bytes : SizeFlagVal<4>;
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// Load / store index mode.
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class IndexMode<bits<2> val> {
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bits<2> Value = val;
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}
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def IndexModeNone : IndexMode<0>;
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def IndexModePre : IndexMode<1>;
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def IndexModePost : IndexMode<2>;
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//===----------------------------------------------------------------------===//
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// ARM Instruction templates.
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//
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// ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode.
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class ARMPat<dag pattern, dag result> : Pat<pattern, result> {
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list<Predicate> Predicates = [IsARM];
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}
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class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> {
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list<Predicate> Predicates = [IsARM, HasV5TE];
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}
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class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> {
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list<Predicate> Predicates = [IsARM, HasV6];
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}
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class InstARM<bits<4> opcod, AddrMode am, SizeFlagVal sz, IndexMode im,
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dag ops, string asmstr, string cstr>
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: Instruction {
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let Namespace = "ARM";
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bits<4> Opcode = opcod;
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AddrMode AM = am;
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bits<4> AddrModeBits = AM.Value;
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SizeFlagVal SZ = sz;
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bits<3> SizeFlag = SZ.Value;
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IndexMode IM = im;
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bits<2> IndexModeBits = IM.Value;
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dag OperandList = ops;
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let AsmString = asmstr;
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let Constraints = cstr;
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}
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class PseudoInst<dag ops, string asm, list<dag> pattern>
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: InstARM<0, AddrModeNone, SizeSpecial, IndexModeNone, ops, asm, ""> {
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let Pattern = pattern;
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}
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class I<dag ops, AddrMode am, SizeFlagVal sz, IndexMode im,
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string asm, string cstr, list<dag> pattern>
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// FIXME: Set all opcodes to 0 for now.
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: InstARM<0, am, sz, im, ops, asm, cstr> {
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let Pattern = pattern;
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list<Predicate> Predicates = [IsARM];
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}
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class AI<dag ops, string asm, list<dag> pattern>
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: I<ops, AddrModeNone, Size4Bytes, IndexModeNone, asm, "", pattern>;
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class AI1<dag ops, string asm, list<dag> pattern>
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: I<ops, AddrMode1, Size4Bytes, IndexModeNone, asm, "", pattern>;
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class AI2<dag ops, string asm, list<dag> pattern>
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: I<ops, AddrMode2, Size4Bytes, IndexModeNone, asm, "", pattern>;
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class AI3<dag ops, string asm, list<dag> pattern>
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: I<ops, AddrMode3, Size4Bytes, IndexModeNone, asm, "", pattern>;
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class AI4<dag ops, string asm, list<dag> pattern>
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: I<ops, AddrMode4, Size4Bytes, IndexModeNone, asm, "", pattern>;
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class AIx2<dag ops, string asm, list<dag> pattern>
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: I<ops, AddrModeNone, Size8Bytes, IndexModeNone, asm, "", pattern>;
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// Pre-indexed ops
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class AI2pr<dag ops, string asm, string cstr, list<dag> pattern>
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: I<ops, AddrMode2, Size4Bytes, IndexModePre, asm, cstr, pattern>;
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class AI3pr<dag ops, string asm, string cstr, list<dag> pattern>
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: I<ops, AddrMode3, Size4Bytes, IndexModePre, asm, cstr, pattern>;
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// Post-indexed ops
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class AI2po<dag ops, string asm, string cstr, list<dag> pattern>
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: I<ops, AddrMode2, Size4Bytes, IndexModePost, asm, cstr, pattern>;
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class AI3po<dag ops, string asm, string cstr, list<dag> pattern>
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: I<ops, AddrMode3, Size4Bytes, IndexModePost, asm, cstr, pattern>;
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// BR_JT instructions
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class JTI<dag ops, string asm, list<dag> pattern>
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: I<ops, AddrModeNone, SizeSpecial, IndexModeNone, asm, "", pattern>;
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class JTI1<dag ops, string asm, list<dag> pattern>
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: I<ops, AddrMode1, SizeSpecial, IndexModeNone, asm, "", pattern>;
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class JTI2<dag ops, string asm, list<dag> pattern>
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: I<ops, AddrMode2, SizeSpecial, IndexModeNone, asm, "", pattern>;
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class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
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class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
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/// AI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
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/// binop that produces a value.
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multiclass AI1_bin_irs<string opc, PatFrag opnode> {
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def ri : AI1<(ops GPR:$dst, GPR:$a, so_imm:$b),
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!strconcat(opc, " $dst, $a, $b"),
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[(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>;
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def rr : AI1<(ops GPR:$dst, GPR:$a, GPR:$b),
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!strconcat(opc, " $dst, $a, $b"),
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[(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>;
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def rs : AI1<(ops GPR:$dst, GPR:$a, so_reg:$b),
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!strconcat(opc, " $dst, $a, $b"),
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[(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>;
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}
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/// AI1_bin0_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns.
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/// Similar to AI1_bin_irs except the instruction does not produce a result.
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multiclass AI1_bin0_irs<string opc, PatFrag opnode> {
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def ri : AI1<(ops GPR:$a, so_imm:$b),
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!strconcat(opc, " $a, $b"),
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[(opnode GPR:$a, so_imm:$b)]>;
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def rr : AI1<(ops GPR:$a, GPR:$b),
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!strconcat(opc, " $a, $b"),
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[(opnode GPR:$a, GPR:$b)]>;
|
|
def rs : AI1<(ops GPR:$a, so_reg:$b),
|
|
!strconcat(opc, " $a, $b"),
|
|
[(opnode GPR:$a, so_reg:$b)]>;
|
|
}
|
|
|
|
/// AI1_bin_is - Defines a set of (op r, {so_imm|so_reg}) patterns for a binop.
|
|
multiclass AI1_bin_is<string opc, PatFrag opnode> {
|
|
def ri : AI1<(ops GPR:$dst, GPR:$a, so_imm:$b),
|
|
!strconcat(opc, " $dst, $a, $b"),
|
|
[(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>;
|
|
def rs : AI1<(ops GPR:$dst, GPR:$a, so_reg:$b),
|
|
!strconcat(opc, " $dst, $a, $b"),
|
|
[(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>;
|
|
}
|
|
|
|
/// AI1_unary_irs - Defines a set of (op {so_imm|r|so_reg}) patterns for unary
|
|
/// ops.
|
|
multiclass AI1_unary_irs<string opc, PatFrag opnode> {
|
|
def i : AI1<(ops GPR:$dst, so_imm:$a),
|
|
!strconcat(opc, " $dst, $a"),
|
|
[(set GPR:$dst, (opnode so_imm:$a))]>;
|
|
def r : AI1<(ops GPR:$dst, GPR:$a),
|
|
!strconcat(opc, " $dst, $a"),
|
|
[(set GPR:$dst, (opnode GPR:$a))]>;
|
|
def s : AI1<(ops GPR:$dst, so_reg:$a),
|
|
!strconcat(opc, " $dst, $a"),
|
|
[(set GPR:$dst, (opnode so_reg:$a))]>;
|
|
}
|
|
|
|
/// AI_unary_rrot - A unary operation with two forms: one whose operand is a
|
|
/// register and one whose operand is a register rotated by 8/16/24.
|
|
multiclass AI_unary_rrot<string opc, PatFrag opnode> {
|
|
def r : AI<(ops GPR:$dst, GPR:$Src),
|
|
!strconcat(opc, " $dst, $Src"),
|
|
[(set GPR:$dst, (opnode GPR:$Src))]>, Requires<[IsARM, HasV6]>;
|
|
def r_rot : AI<(ops GPR:$dst, GPR:$Src, i32imm:$rot),
|
|
!strconcat(opc, " $dst, $Src, ror $rot"),
|
|
[(set GPR:$dst, (opnode (rotr GPR:$Src, rot_imm:$rot)))]>,
|
|
Requires<[IsARM, HasV6]>;
|
|
}
|
|
|
|
/// AI_bin_rrot - A binary operation with two forms: one whose operand is a
|
|
/// register and one whose operand is a register rotated by 8/16/24.
|
|
multiclass AI_bin_rrot<string opc, PatFrag opnode> {
|
|
def rr : AI<(ops GPR:$dst, GPR:$LHS, GPR:$RHS),
|
|
!strconcat(opc, " $dst, $LHS, $RHS"),
|
|
[(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>,
|
|
Requires<[IsARM, HasV6]>;
|
|
def rr_rot : AI<(ops GPR:$dst, GPR:$LHS, GPR:$RHS, i32imm:$rot),
|
|
!strconcat(opc, " $dst, $LHS, $RHS, ror $rot"),
|
|
[(set GPR:$dst, (opnode GPR:$LHS,
|
|
(rotr GPR:$RHS, rot_imm:$rot)))]>,
|
|
Requires<[IsARM, HasV6]>;
|
|
}
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Instructions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Miscellaneous Instructions.
|
|
//
|
|
def IMPLICIT_DEF_GPR :
|
|
PseudoInst<(ops GPR:$rD),
|
|
"@ IMPLICIT_DEF_GPR $rD",
|
|
[(set GPR:$rD, (undef))]>;
|
|
|
|
|
|
/// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
|
|
/// the function. The first operand is the ID# for this instruction, the second
|
|
/// is the index into the MachineConstantPool that this is, the third is the
|
|
/// size in bytes of this constant pool entry.
|
|
def CONSTPOOL_ENTRY :
|
|
PseudoInst<(ops cpinst_operand:$instid, cpinst_operand:$cpidx, i32imm:$size),
|
|
"${instid:label} ${cpidx:cpentry}", []>;
|
|
|
|
def ADJCALLSTACKUP :
|
|
PseudoInst<(ops i32imm:$amt),
|
|
"@ ADJCALLSTACKUP $amt",
|
|
[(ARMcallseq_end imm:$amt)]>, Imp<[SP],[SP]>;
|
|
|
|
def ADJCALLSTACKDOWN :
|
|
PseudoInst<(ops i32imm:$amt),
|
|
"@ ADJCALLSTACKDOWN $amt",
|
|
[(ARMcallseq_start imm:$amt)]>, Imp<[SP],[SP]>;
|
|
|
|
def DWARF_LOC :
|
|
PseudoInst<(ops i32imm:$line, i32imm:$col, i32imm:$file),
|
|
".loc $file, $line, $col",
|
|
[(dwarf_loc (i32 imm:$line), (i32 imm:$col), (i32 imm:$file))]>;
|
|
|
|
def PICADD : AI1<(ops GPR:$dst, GPR:$a, pclabel:$cp),
|
|
"$cp:\n\tadd $dst, pc, $a",
|
|
[(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
|
|
let AddedComplexity = 10 in
|
|
def PICLD : AI2<(ops GPR:$dst, addrmodepc:$addr),
|
|
"${addr:label}:\n\tldr $dst, $addr",
|
|
[(set GPR:$dst, (load addrmodepc:$addr))]>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Control Flow Instructions.
|
|
//
|
|
|
|
let isReturn = 1, isTerminator = 1 in
|
|
def BX_RET : AI<(ops), "bx lr", [(ARMretflag)]>;
|
|
|
|
// FIXME: remove when we have a way to marking a MI with these properties.
|
|
let isLoad = 1, isReturn = 1, isTerminator = 1 in
|
|
def LDM_RET : AI4<(ops addrmode4:$addr, reglist:$dst1, variable_ops),
|
|
"ldm${addr:submode} $addr, $dst1",
|
|
[]>;
|
|
|
|
let isCall = 1, noResults = 1,
|
|
Defs = [R0, R1, R2, R3, R12, LR,
|
|
D0, D1, D2, D3, D4, D5, D6, D7] in {
|
|
def BL : AI<(ops i32imm:$func, variable_ops),
|
|
"bl ${func:call}",
|
|
[(ARMcall tglobaladdr:$func)]>;
|
|
// ARMv5T and above
|
|
def BLX : AI<(ops GPR:$dst, variable_ops),
|
|
"blx $dst",
|
|
[(ARMcall GPR:$dst)]>, Requires<[IsARM, HasV5T]>;
|
|
// ARMv4T
|
|
def BX : AIx2<(ops GPR:$dst, variable_ops),
|
|
"mov lr, pc\n\tbx $dst",
|
|
[(ARMcall_nolink GPR:$dst)]>;
|
|
}
|
|
|
|
let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
|
|
def B : AI<(ops brtarget:$dst), "b $dst",
|
|
[(br bb:$dst)]>;
|
|
|
|
def BR_JTr : JTI<(ops GPR:$dst, jtblock_operand:$jt, i32imm:$id),
|
|
"mov pc, $dst \n$jt",
|
|
[(ARMbrjt GPR:$dst, tjumptable:$jt, imm:$id)]>;
|
|
def BR_JTm : JTI2<(ops addrmode2:$dst, jtblock_operand:$jt, i32imm:$id),
|
|
"ldr pc, $dst \n$jt",
|
|
[(ARMbrjt (i32 (load addrmode2:$dst)), tjumptable:$jt,
|
|
imm:$id)]>;
|
|
def BR_JTadd : JTI1<(ops GPR:$dst, GPR:$idx, jtblock_operand:$jt, i32imm:$id),
|
|
"add pc, $dst, $idx \n$jt",
|
|
[(ARMbrjt (add GPR:$dst, GPR:$idx), tjumptable:$jt,
|
|
imm:$id)]>;
|
|
}
|
|
|
|
let isBranch = 1, isTerminator = 1, noResults = 1, isBarrier = 1 in
|
|
def Bcc : AI<(ops brtarget:$dst, CCOp:$cc), "b$cc $dst",
|
|
[(ARMbrcond bb:$dst, imm:$cc)]>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Load / store Instructions.
|
|
//
|
|
|
|
// Load
|
|
let isLoad = 1 in {
|
|
def LDR : AI2<(ops GPR:$dst, addrmode2:$addr),
|
|
"ldr $dst, $addr",
|
|
[(set GPR:$dst, (load addrmode2:$addr))]>;
|
|
|
|
// Loads with zero extension
|
|
def LDRH : AI3<(ops GPR:$dst, addrmode3:$addr),
|
|
"ldrh $dst, $addr",
|
|
[(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>;
|
|
|
|
def LDRB : AI2<(ops GPR:$dst, addrmode2:$addr),
|
|
"ldrb $dst, $addr",
|
|
[(set GPR:$dst, (zextloadi8 addrmode2:$addr))]>;
|
|
|
|
// Loads with sign extension
|
|
def LDRSH : AI3<(ops GPR:$dst, addrmode3:$addr),
|
|
"ldrsh $dst, $addr",
|
|
[(set GPR:$dst, (sextloadi16 addrmode3:$addr))]>;
|
|
|
|
def LDRSB : AI3<(ops GPR:$dst, addrmode3:$addr),
|
|
"ldrsb $dst, $addr",
|
|
[(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>;
|
|
|
|
// Load doubleword
|
|
def LDRD : AI3<(ops GPR:$dst, addrmode3:$addr),
|
|
"ldrd $dst, $addr",
|
|
[]>, Requires<[IsARM, HasV5T]>;
|
|
|
|
// Indexed loads
|
|
def LDR_PRE : AI2pr<(ops GPR:$dst, GPR:$base_wb, addrmode2:$addr),
|
|
"ldr $dst, $addr!", "$addr.base = $base_wb", []>;
|
|
|
|
def LDR_POST : AI2po<(ops GPR:$dst, GPR:$base_wb, GPR:$base, am2offset:$offset),
|
|
"ldr $dst, [$base], $offset", "$base = $base_wb", []>;
|
|
|
|
def LDRH_PRE : AI3pr<(ops GPR:$dst, GPR:$base_wb, addrmode3:$addr),
|
|
"ldrh $dst, $addr!", "$addr.base = $base_wb", []>;
|
|
|
|
def LDRH_POST : AI3po<(ops GPR:$dst, GPR:$base_wb, GPR:$base,am3offset:$offset),
|
|
"ldrh $dst, [$base], $offset", "$base = $base_wb", []>;
|
|
|
|
def LDRB_PRE : AI2pr<(ops GPR:$dst, GPR:$base_wb, addrmode2:$addr),
|
|
"ldrb $dst, $addr!", "$addr.base = $base_wb", []>;
|
|
|
|
def LDRB_POST : AI2po<(ops GPR:$dst, GPR:$base_wb, GPR:$base,am2offset:$offset),
|
|
"ldrb $dst, [$base], $offset", "$base = $base_wb", []>;
|
|
|
|
def LDRSH_PRE : AI3pr<(ops GPR:$dst, GPR:$base_wb, addrmode3:$addr),
|
|
"ldrsh $dst, $addr!", "$addr.base = $base_wb", []>;
|
|
|
|
def LDRSH_POST: AI3po<(ops GPR:$dst, GPR:$base_wb, GPR:$base,am3offset:$offset),
|
|
"ldrsh $dst, [$base], $offset", "$base = $base_wb", []>;
|
|
|
|
def LDRSB_PRE : AI3pr<(ops GPR:$dst, GPR:$base_wb, addrmode3:$addr),
|
|
"ldrsb $dst, $addr!", "$addr.base = $base_wb", []>;
|
|
|
|
def LDRSB_POST: AI3po<(ops GPR:$dst, GPR:$base_wb, GPR:$base,am3offset:$offset),
|
|
"ldrsb $dst, [$base], $offset", "$base = $base_wb", []>;
|
|
} // isLoad
|
|
|
|
// Store
|
|
let isStore = 1 in {
|
|
def STR : AI2<(ops GPR:$src, addrmode2:$addr),
|
|
"str $src, $addr",
|
|
[(store GPR:$src, addrmode2:$addr)]>;
|
|
|
|
// Stores with truncate
|
|
def STRH : AI3<(ops GPR:$src, addrmode3:$addr),
|
|
"strh $src, $addr",
|
|
[(truncstorei16 GPR:$src, addrmode3:$addr)]>;
|
|
|
|
def STRB : AI2<(ops GPR:$src, addrmode2:$addr),
|
|
"strb $src, $addr",
|
|
[(truncstorei8 GPR:$src, addrmode2:$addr)]>;
|
|
|
|
// Store doubleword
|
|
def STRD : AI3<(ops GPR:$src, addrmode3:$addr),
|
|
"strd $src, $addr",
|
|
[]>, Requires<[IsARM, HasV5T]>;
|
|
|
|
// Indexed stores
|
|
def STR_PRE : AI2pr<(ops GPR:$base_wb, GPR:$src, GPR:$base, am2offset:$offset),
|
|
"str $src, [$base, $offset]!", "$base = $base_wb",
|
|
[(set GPR:$base_wb,
|
|
(pre_store GPR:$src, GPR:$base, am2offset:$offset))]>;
|
|
|
|
def STR_POST : AI2po<(ops GPR:$base_wb, GPR:$src, GPR:$base,am2offset:$offset),
|
|
"str $src, [$base], $offset", "$base = $base_wb",
|
|
[(set GPR:$base_wb,
|
|
(post_store GPR:$src, GPR:$base, am2offset:$offset))]>;
|
|
|
|
def STRH_PRE : AI3pr<(ops GPR:$base_wb, GPR:$src, GPR:$base,am3offset:$offset),
|
|
"strh $src, [$base, $offset]!", "$base = $base_wb",
|
|
[(set GPR:$base_wb,
|
|
(pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>;
|
|
|
|
def STRH_POST: AI3po<(ops GPR:$base_wb, GPR:$src, GPR:$base,am3offset:$offset),
|
|
"strh $src, [$base], $offset", "$base = $base_wb",
|
|
[(set GPR:$base_wb, (post_truncsti16 GPR:$src,
|
|
GPR:$base, am3offset:$offset))]>;
|
|
|
|
def STRB_PRE : AI2pr<(ops GPR:$base_wb, GPR:$src, GPR:$base,am2offset:$offset),
|
|
"strb $src, [$base, $offset]!", "$base = $base_wb",
|
|
[(set GPR:$base_wb, (pre_truncsti8 GPR:$src,
|
|
GPR:$base, am2offset:$offset))]>;
|
|
|
|
def STRB_POST: AI2po<(ops GPR:$base_wb, GPR:$src, GPR:$base,am2offset:$offset),
|
|
"strb $src, [$base], $offset", "$base = $base_wb",
|
|
[(set GPR:$base_wb, (post_truncsti8 GPR:$src,
|
|
GPR:$base, am2offset:$offset))]>;
|
|
} // isStore
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Load / store multiple Instructions.
|
|
//
|
|
|
|
let isLoad = 1 in
|
|
def LDM : AI4<(ops addrmode4:$addr, reglist:$dst1, variable_ops),
|
|
"ldm${addr:submode} $addr, $dst1",
|
|
[]>;
|
|
|
|
let isStore = 1 in
|
|
def STM : AI4<(ops addrmode4:$addr, reglist:$src1, variable_ops),
|
|
"stm${addr:submode} $addr, $src1",
|
|
[]>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Move Instructions.
|
|
//
|
|
|
|
def MOVrr : AI1<(ops GPR:$dst, GPR:$src),
|
|
"mov $dst, $src", []>;
|
|
def MOVrs : AI1<(ops GPR:$dst, so_reg:$src),
|
|
"mov $dst, $src", [(set GPR:$dst, so_reg:$src)]>;
|
|
def MOVri : AI1<(ops GPR:$dst, so_imm:$src),
|
|
"mov $dst, $src", [(set GPR:$dst, so_imm:$src)]>;
|
|
|
|
// These aren't really mov instructions, but we have to define them this way
|
|
// due to flag operands.
|
|
|
|
def MOVsrl_flag : AI1<(ops GPR:$dst, GPR:$src),
|
|
"movs $dst, $src, lsr #1",
|
|
[(set GPR:$dst, (ARMsrl_flag GPR:$src))]>;
|
|
def MOVsra_flag : AI1<(ops GPR:$dst, GPR:$src),
|
|
"movs $dst, $src, asr #1",
|
|
[(set GPR:$dst, (ARMsra_flag GPR:$src))]>;
|
|
def MOVrrx : AI1<(ops GPR:$dst, GPR:$src),
|
|
"mov $dst, $src, rrx",
|
|
[(set GPR:$dst, (ARMrrx GPR:$src))]>;
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Extend Instructions.
|
|
//
|
|
|
|
// Sign extenders
|
|
|
|
defm SXTB : AI_unary_rrot<"sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
|
|
defm SXTH : AI_unary_rrot<"sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
|
|
|
|
defm SXTAB : AI_bin_rrot<"sxtab",
|
|
BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
|
|
defm SXTAH : AI_bin_rrot<"sxtah",
|
|
BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
|
|
|
|
// TODO: SXT(A){B|H}16
|
|
|
|
// Zero extenders
|
|
|
|
let AddedComplexity = 16 in {
|
|
defm UXTB : AI_unary_rrot<"uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
|
|
defm UXTH : AI_unary_rrot<"uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
|
|
defm UXTB16 : AI_unary_rrot<"uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
|
|
|
|
def : ARMV6Pat<(and (shl GPR:$Src, 8), 0xFF00FF),
|
|
(UXTB16r_rot GPR:$Src, 24)>;
|
|
def : ARMV6Pat<(and (srl GPR:$Src, 8), 0xFF00FF),
|
|
(UXTB16r_rot GPR:$Src, 8)>;
|
|
|
|
defm UXTAB : AI_bin_rrot<"uxtab",
|
|
BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
|
|
defm UXTAH : AI_bin_rrot<"uxtah",
|
|
BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
|
|
}
|
|
|
|
// This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
|
|
//defm UXTAB16 : xxx<"uxtab16", 0xff00ff>;
|
|
|
|
// TODO: UXT(A){B|H}16
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Arithmetic Instructions.
|
|
//
|
|
|
|
defm ADD : AI1_bin_irs<"add" , BinOpFrag<(add node:$LHS, node:$RHS)>>;
|
|
defm ADDS : AI1_bin_irs<"adds", BinOpFrag<(addc node:$LHS, node:$RHS)>>;
|
|
defm ADC : AI1_bin_irs<"adc" , BinOpFrag<(adde node:$LHS, node:$RHS)>>;
|
|
defm SUB : AI1_bin_irs<"sub" , BinOpFrag<(sub node:$LHS, node:$RHS)>>;
|
|
defm SUBS : AI1_bin_irs<"subs", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
|
|
defm SBC : AI1_bin_irs<"sbc" , BinOpFrag<(sube node:$LHS, node:$RHS)>>;
|
|
|
|
// These don't define reg/reg forms, because they are handled above.
|
|
defm RSB : AI1_bin_is <"rsb" , BinOpFrag<(sub node:$RHS, node:$LHS)>>;
|
|
defm RSBS : AI1_bin_is <"rsbs", BinOpFrag<(subc node:$RHS, node:$LHS)>>;
|
|
defm RSC : AI1_bin_is <"rsc" , BinOpFrag<(sube node:$RHS, node:$LHS)>>;
|
|
|
|
// (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
|
|
def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
|
|
(SUBri GPR:$src, so_imm_neg:$imm)>;
|
|
|
|
//def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
|
|
// (SUBSri GPR:$src, so_imm_neg:$imm)>;
|
|
//def : ARMPat<(adde GPR:$src, so_imm_neg:$imm),
|
|
// (SBCri GPR:$src, so_imm_neg:$imm)>;
|
|
|
|
// Note: These are implemented in C++ code, because they have to generate
|
|
// ADD/SUBrs instructions, which use a complex pattern that a xform function
|
|
// cannot produce.
|
|
// (mul X, 2^n+1) -> (add (X << n), X)
|
|
// (mul X, 2^n-1) -> (rsb X, (X << n))
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Bitwise Instructions.
|
|
//
|
|
|
|
defm AND : AI1_bin_irs<"and", BinOpFrag<(and node:$LHS, node:$RHS)>>;
|
|
defm ORR : AI1_bin_irs<"orr", BinOpFrag<(or node:$LHS, node:$RHS)>>;
|
|
defm EOR : AI1_bin_irs<"eor", BinOpFrag<(xor node:$LHS, node:$RHS)>>;
|
|
defm BIC : AI1_bin_irs<"bic", BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
|
|
|
|
defm MVN : AI1_unary_irs<"mvn", not>;
|
|
|
|
def : ARMPat<(i32 so_imm_not:$imm),
|
|
(MVNi so_imm_not:$imm)>;
|
|
|
|
def : ARMPat<(and GPR:$src, so_imm_not:$imm),
|
|
(BICri GPR:$src, so_imm_not:$imm)>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Multiply Instructions.
|
|
//
|
|
|
|
// AI_orr - Defines a (op r, r) pattern.
|
|
class AI_orr<string opc, SDNode opnode>
|
|
: AI<(ops GPR:$dst, GPR:$a, GPR:$b),
|
|
!strconcat(opc, " $dst, $a, $b"),
|
|
[(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>;
|
|
|
|
// AI_oorr - Defines a (op (op r, r), r) pattern.
|
|
class AI_oorr<string opc, SDNode opnode1, SDNode opnode2>
|
|
: AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$c),
|
|
!strconcat(opc, " $dst, $a, $b, $c"),
|
|
[(set GPR:$dst, (opnode1 (opnode2 GPR:$a, GPR:$b), GPR:$c))]>;
|
|
|
|
def MUL : AI_orr<"mul", mul>;
|
|
def MLA : AI_oorr<"mla", add, mul>;
|
|
|
|
// Extra precision multiplies with low / high results
|
|
def SMULL : AI<(ops GPR:$ldst, GPR:$hdst, GPR:$a, GPR:$b),
|
|
"smull $ldst, $hdst, $a, $b",
|
|
[]>;
|
|
|
|
def UMULL : AI<(ops GPR:$ldst, GPR:$hdst, GPR:$a, GPR:$b),
|
|
"umull $ldst, $hdst, $a, $b",
|
|
[]>;
|
|
|
|
// Multiply + accumulate
|
|
def SMLAL : AI<(ops GPR:$ldst, GPR:$hdst, GPR:$a, GPR:$b),
|
|
"smlal $ldst, $hdst, $a, $b",
|
|
[]>;
|
|
|
|
def UMLAL : AI<(ops GPR:$ldst, GPR:$hdst, GPR:$a, GPR:$b),
|
|
"umlal $ldst, $hdst, $a, $b",
|
|
[]>;
|
|
|
|
def UMAAL : AI<(ops GPR:$ldst, GPR:$hdst, GPR:$a, GPR:$b),
|
|
"umaal $ldst, $hdst, $a, $b",
|
|
[]>, Requires<[IsARM, HasV6]>;
|
|
|
|
// Most significant word multiply
|
|
def SMMUL : AI_orr<"smmul", mulhs>, Requires<[IsARM, HasV6]>;
|
|
def SMMLA : AI_oorr<"smmla", add, mulhs>, Requires<[IsARM, HasV6]>;
|
|
|
|
|
|
def SMMLS : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$c),
|
|
"smmls $dst, $a, $b, $c",
|
|
[(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>,
|
|
Requires<[IsARM, HasV6]>;
|
|
|
|
multiclass AI_smul<string opc, PatFrag opnode> {
|
|
def BB : AI<(ops GPR:$dst, GPR:$a, GPR:$b),
|
|
!strconcat(opc, "bb $dst, $a, $b"),
|
|
[(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
|
|
(sext_inreg GPR:$b, i16)))]>,
|
|
Requires<[IsARM, HasV5TE]>;
|
|
def BT : AI<(ops GPR:$dst, GPR:$a, GPR:$b),
|
|
!strconcat(opc, "bt $dst, $a, $b"),
|
|
[(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
|
|
(sra GPR:$b, 16)))]>,
|
|
Requires<[IsARM, HasV5TE]>;
|
|
def TB : AI<(ops GPR:$dst, GPR:$a, GPR:$b),
|
|
!strconcat(opc, "tb $dst, $a, $b"),
|
|
[(set GPR:$dst, (opnode (sra GPR:$a, 16),
|
|
(sext_inreg GPR:$b, i16)))]>,
|
|
Requires<[IsARM, HasV5TE]>;
|
|
def TT : AI<(ops GPR:$dst, GPR:$a, GPR:$b),
|
|
!strconcat(opc, "tt $dst, $a, $b"),
|
|
[(set GPR:$dst, (opnode (sra GPR:$a, 16),
|
|
(sra GPR:$b, 16)))]>,
|
|
Requires<[IsARM, HasV5TE]>;
|
|
def WB : AI<(ops GPR:$dst, GPR:$a, GPR:$b),
|
|
!strconcat(opc, "wb $dst, $a, $b"),
|
|
[(set GPR:$dst, (sra (opnode GPR:$a,
|
|
(sext_inreg GPR:$b, i16)), 16))]>,
|
|
Requires<[IsARM, HasV5TE]>;
|
|
def WT : AI<(ops GPR:$dst, GPR:$a, GPR:$b),
|
|
!strconcat(opc, "wt $dst, $a, $b"),
|
|
[(set GPR:$dst, (sra (opnode GPR:$a,
|
|
(sra GPR:$b, 16)), 16))]>,
|
|
Requires<[IsARM, HasV5TE]>;
|
|
}
|
|
|
|
multiclass AI_smla<string opc, PatFrag opnode> {
|
|
def BB : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$acc),
|
|
!strconcat(opc, "bb $dst, $a, $b, $acc"),
|
|
[(set GPR:$dst, (add GPR:$acc,
|
|
(opnode (sext_inreg GPR:$a, i16),
|
|
(sext_inreg GPR:$b, i16))))]>,
|
|
Requires<[IsARM, HasV5TE]>;
|
|
def BT : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$acc),
|
|
!strconcat(opc, "bt $dst, $a, $b, $acc"),
|
|
[(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),
|
|
(sra GPR:$b, 16))))]>,
|
|
Requires<[IsARM, HasV5TE]>;
|
|
def TB : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$acc),
|
|
!strconcat(opc, "tb $dst, $a, $b, $acc"),
|
|
[(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, 16),
|
|
(sext_inreg GPR:$b, i16))))]>,
|
|
Requires<[IsARM, HasV5TE]>;
|
|
def TT : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$acc),
|
|
!strconcat(opc, "tt $dst, $a, $b, $acc"),
|
|
[(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, 16),
|
|
(sra GPR:$b, 16))))]>,
|
|
Requires<[IsARM, HasV5TE]>;
|
|
|
|
def WB : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$acc),
|
|
!strconcat(opc, "wb $dst, $a, $b, $acc"),
|
|
[(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
|
|
(sext_inreg GPR:$b, i16)), 16)))]>,
|
|
Requires<[IsARM, HasV5TE]>;
|
|
def WT : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$acc),
|
|
!strconcat(opc, "wt $dst, $a, $b, $acc"),
|
|
[(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
|
|
(sra GPR:$b, 16)), 16)))]>,
|
|
Requires<[IsARM, HasV5TE]>;
|
|
}
|
|
|
|
defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
|
|
defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
|
|
|
|
// TODO: Halfword multiple accumulate long: SMLAL<x><y>
|
|
// TODO: Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Misc. Arithmetic Instructions.
|
|
//
|
|
|
|
def CLZ : AI<(ops GPR:$dst, GPR:$src),
|
|
"clz $dst, $src",
|
|
[(set GPR:$dst, (ctlz GPR:$src))]>, Requires<[IsARM, HasV5T]>;
|
|
|
|
def REV : AI<(ops GPR:$dst, GPR:$src),
|
|
"rev $dst, $src",
|
|
[(set GPR:$dst, (bswap GPR:$src))]>, Requires<[IsARM, HasV6]>;
|
|
|
|
def REV16 : AI<(ops GPR:$dst, GPR:$src),
|
|
"rev16 $dst, $src",
|
|
[(set GPR:$dst,
|
|
(or (and (srl GPR:$src, 8), 0xFF),
|
|
(or (and (shl GPR:$src, 8), 0xFF00),
|
|
(or (and (srl GPR:$src, 8), 0xFF0000),
|
|
(and (shl GPR:$src, 8), 0xFF000000)))))]>,
|
|
Requires<[IsARM, HasV6]>;
|
|
|
|
def REVSH : AI<(ops GPR:$dst, GPR:$src),
|
|
"revsh $dst, $src",
|
|
[(set GPR:$dst,
|
|
(sext_inreg
|
|
(or (srl (and GPR:$src, 0xFFFF), 8),
|
|
(shl GPR:$src, 8)), i16))]>,
|
|
Requires<[IsARM, HasV6]>;
|
|
|
|
def PKHBT : AI<(ops GPR:$dst, GPR:$src1, GPR:$src2, i32imm:$shamt),
|
|
"pkhbt $dst, $src1, $src2, LSL $shamt",
|
|
[(set GPR:$dst, (or (and GPR:$src1, 0xFFFF),
|
|
(and (shl GPR:$src2, (i32 imm:$shamt)),
|
|
0xFFFF0000)))]>,
|
|
Requires<[IsARM, HasV6]>;
|
|
|
|
// Alternate cases for PKHBT where identities eliminate some nodes.
|
|
def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)),
|
|
(PKHBT GPR:$src1, GPR:$src2, 0)>;
|
|
def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)),
|
|
(PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>;
|
|
|
|
|
|
def PKHTB : AI<(ops GPR:$dst, GPR:$src1, GPR:$src2, i32imm:$shamt),
|
|
"pkhtb $dst, $src1, $src2, ASR $shamt",
|
|
[(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000),
|
|
(and (sra GPR:$src2, imm16_31:$shamt),
|
|
0xFFFF)))]>, Requires<[IsARM, HasV6]>;
|
|
|
|
// Alternate cases for PKHTB where identities eliminate some nodes. Note that
|
|
// a shift amount of 0 is *not legal* here, it is PKHBT instead.
|
|
def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, 16)),
|
|
(PKHTB GPR:$src1, GPR:$src2, 16)>;
|
|
def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
|
|
(and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)),
|
|
(PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>;
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Comparison Instructions...
|
|
//
|
|
|
|
defm CMP : AI1_bin0_irs<"cmp", BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
|
|
defm CMN : AI1_bin0_irs<"cmn", BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
|
|
|
|
def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
|
|
(CMNri GPR:$src, so_imm_neg:$imm)>;
|
|
|
|
// Note that TST/TEQ don't set all the same flags that CMP does!
|
|
def TSTrr : AI1<(ops GPR:$a, so_reg:$b), "tst $a, $b", []>;
|
|
def TSTri : AI1<(ops GPR:$a, so_imm:$b), "tst $a, $b", []>;
|
|
def TEQrr : AI1<(ops GPR:$a, so_reg:$b), "teq $a, $b", []>;
|
|
def TEQri : AI1<(ops GPR:$a, so_imm:$b), "teq $a, $b", []>;
|
|
|
|
// Conditional moves
|
|
def MOVCCr : AI<(ops GPR:$dst, GPR:$false, GPR:$true, CCOp:$cc),
|
|
"mov$cc $dst, $true",
|
|
[(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc))]>,
|
|
RegConstraint<"$false = $dst">;
|
|
|
|
def MOVCCs : AI<(ops GPR:$dst, GPR:$false, so_reg:$true, CCOp:$cc),
|
|
"mov$cc $dst, $true",
|
|
[(set GPR:$dst, (ARMcmov GPR:$false, so_reg:$true,imm:$cc))]>,
|
|
RegConstraint<"$false = $dst">;
|
|
|
|
def MOVCCi : AI<(ops GPR:$dst, GPR:$false, so_imm:$true, CCOp:$cc),
|
|
"mov$cc $dst, $true",
|
|
[(set GPR:$dst, (ARMcmov GPR:$false, so_imm:$true,imm:$cc))]>,
|
|
RegConstraint<"$false = $dst">;
|
|
|
|
|
|
// LEApcrel - Load a pc-relative address into a register without offending the
|
|
// assembler.
|
|
def LEApcrel : AI1<(ops GPR:$dst, i32imm:$label),
|
|
!strconcat(!strconcat(".set PCRELV${:uid}, ($label-(",
|
|
"${:private}PCRELL${:uid}+8))\n"),
|
|
!strconcat("${:private}PCRELL${:uid}:\n\t",
|
|
"add $dst, pc, #PCRELV${:uid}")),
|
|
[]>;
|
|
|
|
def LEApcrelJT : AI1<(ops GPR:$dst, i32imm:$label, i32imm:$id),
|
|
!strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(",
|
|
"${:private}PCRELL${:uid}+8))\n"),
|
|
!strconcat("${:private}PCRELL${:uid}:\n\t",
|
|
"add $dst, pc, #PCRELV${:uid}")),
|
|
[]>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Non-Instruction Patterns
|
|
//
|
|
|
|
// ConstantPool, GlobalAddress, and JumpTable
|
|
def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>;
|
|
def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
|
|
def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
|
|
(LEApcrelJT tjumptable:$dst, imm:$id)>;
|
|
|
|
// Large immediate handling.
|
|
|
|
// Two piece so_imms.
|
|
def : ARMPat<(i32 so_imm2part:$src),
|
|
(ORRri (MOVri (so_imm2part_1 imm:$src)),
|
|
(so_imm2part_2 imm:$src))>;
|
|
|
|
def : ARMPat<(or GPR:$LHS, so_imm2part:$RHS),
|
|
(ORRri (ORRri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
|
|
(so_imm2part_2 imm:$RHS))>;
|
|
def : ARMPat<(xor GPR:$LHS, so_imm2part:$RHS),
|
|
(EORri (EORri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
|
|
(so_imm2part_2 imm:$RHS))>;
|
|
|
|
// TODO: add,sub,and, 3-instr forms?
|
|
|
|
|
|
// Direct calls
|
|
def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>;
|
|
|
|
// zextload i1 -> zextload i8
|
|
def : ARMPat<(zextloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
|
|
|
|
// extload -> zextload
|
|
def : ARMPat<(extloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
|
|
def : ARMPat<(extloadi8 addrmode2:$addr), (LDRB addrmode2:$addr)>;
|
|
def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
|
|
|
|
// truncstore i1 -> truncstore i8
|
|
def : Pat<(truncstorei1 GPR:$src, addrmode2:$dst),
|
|
(STRB GPR:$src, addrmode2:$dst)>;
|
|
def : Pat<(pre_truncsti1 GPR:$src, GPR:$base, am2offset:$offset),
|
|
(STRB_PRE GPR:$src, GPR:$base, am2offset:$offset)>;
|
|
def : Pat<(post_truncsti1 GPR:$src, GPR:$base, am2offset:$offset),
|
|
(STRB_POST GPR:$src, GPR:$base, am2offset:$offset)>;
|
|
|
|
// smul* and smla*
|
|
def : ARMV5TEPat<(mul (sra (shl GPR:$a, 16), 16), (sra (shl GPR:$b, 16), 16)),
|
|
(SMULBB GPR:$a, GPR:$b)>;
|
|
def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
|
|
(SMULBB GPR:$a, GPR:$b)>;
|
|
def : ARMV5TEPat<(mul (sra (shl GPR:$a, 16), 16), (sra GPR:$b, 16)),
|
|
(SMULBT GPR:$a, GPR:$b)>;
|
|
def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, 16)),
|
|
(SMULBT GPR:$a, GPR:$b)>;
|
|
def : ARMV5TEPat<(mul (sra GPR:$a, 16), (sra (shl GPR:$b, 16), 16)),
|
|
(SMULTB GPR:$a, GPR:$b)>;
|
|
def : ARMV5TEPat<(mul (sra GPR:$a, 16), sext_16_node:$b),
|
|
(SMULTB GPR:$a, GPR:$b)>;
|
|
def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, 16), 16)), 16),
|
|
(SMULWB GPR:$a, GPR:$b)>;
|
|
def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), 16),
|
|
(SMULWB GPR:$a, GPR:$b)>;
|
|
|
|
def : ARMV5TEPat<(add GPR:$acc,
|
|
(mul (sra (shl GPR:$a, 16), 16),
|
|
(sra (shl GPR:$b, 16), 16))),
|
|
(SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
|
|
def : ARMV5TEPat<(add GPR:$acc,
|
|
(mul sext_16_node:$a, sext_16_node:$b)),
|
|
(SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
|
|
def : ARMV5TEPat<(add GPR:$acc,
|
|
(mul (sra (shl GPR:$a, 16), 16), (sra GPR:$b, 16))),
|
|
(SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
|
|
def : ARMV5TEPat<(add GPR:$acc,
|
|
(mul sext_16_node:$a, (sra GPR:$b, 16))),
|
|
(SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
|
|
def : ARMV5TEPat<(add GPR:$acc,
|
|
(mul (sra GPR:$a, 16), (sra (shl GPR:$b, 16), 16))),
|
|
(SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
|
|
def : ARMV5TEPat<(add GPR:$acc,
|
|
(mul (sra GPR:$a, 16), sext_16_node:$b)),
|
|
(SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
|
|
def : ARMV5TEPat<(add GPR:$acc,
|
|
(sra (mul GPR:$a, (sra (shl GPR:$b, 16), 16)), 16)),
|
|
(SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
|
|
def : ARMV5TEPat<(add GPR:$acc,
|
|
(sra (mul GPR:$a, sext_16_node:$b), 16)),
|
|
(SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Thumb Support
|
|
//
|
|
|
|
include "ARMInstrThumb.td"
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Floating Point Support
|
|
//
|
|
|
|
include "ARMInstrVFP.td"
|