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7c2ef822f7
Summary:
RET, and RET_MM have been replaced by a pseudo named PseudoReturn.
In addition a version with a 64-bit GPR named PseudoReturn64 has been
added.
Instruction selection for a return matches RetRA, which is expanded post
register allocation to PseudoReturn/PseudoReturn64. During MipsAsmPrinter,
this PseudoReturn/PseudoReturn64 are emitted as:
- (JALR64 $zero, $rs) on MIPS64r6
- (JALR $zero, $rs) on MIPS32r6
- (JR_MM $rs) on microMIPS
- (JR $rs) otherwise
On MIPS32r6/MIPS64r6, 'jr $rs' is an alias for 'jalr $zero, $rs'. To aid
development and review (specifically, to ensure all cases of jr are
updated), these aliases are temporarily named 'r6.jr' instead of 'jr'.
A follow up patch will change them back to the correct mnemonic.
Added (JALR $zero, $rs) to MipsNaClELFStreamer's definition of an indirect
jump, and removed it from its definition of a call.
Note: I haven't accounted for MIPS64 in MipsNaClELFStreamer since it's
doesn't appear to account for any MIPS64-specifics.
The return instruction created as part of eh_return expansion is now expanded
using expandRetRA() so we use the right return instruction on MIPS32r6/MIPS64r6
('jalr $zero, $rs').
Also, fixed a misuse of isABI_N64() to detect 64-bit wide registers in
expandEhReturn().
Reviewers: jkolek, vmedic, mseaborn, zoran.jovanovic, dsanders
Reviewed By: dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D4268
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212604 91177308-0d34-0410-b5e6-96231b3b80d8
90 lines
3.2 KiB
LLVM
90 lines
3.2 KiB
LLVM
; RUN: llc -march=mipsel -mcpu=mips32 -asm-show-inst < %s | FileCheck %s -check-prefix=CHECK -check-prefix=NOT-R6
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; RUN: llc -march=mipsel -mcpu=mips32r2 -asm-show-inst < %s | FileCheck %s -check-prefix=CHECK -check-prefix=NOT-R6
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; RUN: llc -march=mipsel -mcpu=mips32r6 -asm-show-inst < %s | FileCheck %s -check-prefix=CHECK -check-prefix=R6
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declare void @llvm.eh.return.i32(i32, i8*)
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declare void @foo(...)
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define i8* @f1(i32 %offset, i8* %handler) {
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entry:
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call void (...)* @foo()
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call void @llvm.eh.return.i32(i32 %offset, i8* %handler)
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unreachable
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; CHECK: f1:
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; CHECK: addiu $sp, $sp, -[[spoffset:[0-9]+]]
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; check that $a0-$a3 are saved on stack.
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; CHECK: sw $4, [[offset0:[0-9]+]]($sp)
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; CHECK: sw $5, [[offset1:[0-9]+]]($sp)
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; CHECK: sw $6, [[offset2:[0-9]+]]($sp)
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; CHECK: sw $7, [[offset3:[0-9]+]]($sp)
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; check that .cfi_offset directives are emitted for $a0-$a3.
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; CHECK: .cfi_offset 4,
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; CHECK: .cfi_offset 5,
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; CHECK: .cfi_offset 6,
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; CHECK: .cfi_offset 7,
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; check that stack adjustment and handler are put in $v1 and $v0.
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; CHECK: move $[[R0:[a-z0-9]+]], $5
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; CHECK: move $[[R1:[a-z0-9]+]], $4
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; CHECK: move $3, $[[R1]]
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; CHECK: move $2, $[[R0]]
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; check that $a0-$a3 are restored from stack.
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; CHECK: lw $4, [[offset0]]($sp)
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; CHECK: lw $5, [[offset1]]($sp)
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; CHECK: lw $6, [[offset2]]($sp)
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; CHECK: lw $7, [[offset3]]($sp)
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; check that stack is adjusted by $v1 and that code returns to address in $v0
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; also check that $25 contains handler value
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; CHECK: addiu $sp, $sp, [[spoffset]]
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; CHECK: move $25, $2
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; CHECK: move $ra, $2
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; NOT-R6: jr $ra # <MCInst #{{[0-9]+}} JR
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; R6: jr $ra # <MCInst #{{[0-9]+}} JALR
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; CHECK: addu $sp, $sp, $3
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}
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define i8* @f2(i32 %offset, i8* %handler) {
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entry:
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call void @llvm.eh.return.i32(i32 %offset, i8* %handler)
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unreachable
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; CHECK: f2:
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; CHECK: addiu $sp, $sp, -[[spoffset:[0-9]+]]
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; check that $a0-$a3 are saved on stack.
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; CHECK: sw $4, [[offset0:[0-9]+]]($sp)
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; CHECK: sw $5, [[offset1:[0-9]+]]($sp)
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; CHECK: sw $6, [[offset2:[0-9]+]]($sp)
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; CHECK: sw $7, [[offset3:[0-9]+]]($sp)
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; check that .cfi_offset directives are emitted for $a0-$a3.
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; CHECK: .cfi_offset 4,
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; CHECK: .cfi_offset 5,
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; CHECK: .cfi_offset 6,
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; CHECK: .cfi_offset 7,
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; check that stack adjustment and handler are put in $v1 and $v0.
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; CHECK: move $3, $4
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; CHECK: move $2, $5
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; check that $a0-$a3 are restored from stack.
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; CHECK: lw $4, [[offset0]]($sp)
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; CHECK: lw $5, [[offset1]]($sp)
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; CHECK: lw $6, [[offset2]]($sp)
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; CHECK: lw $7, [[offset3]]($sp)
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; check that stack is adjusted by $v1 and that code returns to address in $v0
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; also check that $25 contains handler value
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; CHECK: addiu $sp, $sp, [[spoffset]]
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; CHECK: move $25, $2
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; CHECK: move $ra, $2
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; NOT-R6: jr $ra # <MCInst #{{[0-9]+}} JR
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; R6: jr $ra # <MCInst #{{[0-9]+}} JALR
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; CHECK: addu $sp, $sp, $3
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}
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