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8afb08e5b5
Summary: This patch is necessary so that they do not fail on MIPS32r6/MIPS64r6 when -integrated-as is enabled by default and we correctly detect the host CPU. No functional change since these tests are testing the behaviour of the constraint used for the third operand rather than the mnemonic. Depends on D3842 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3843 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209421 91177308-0d34-0410-b5e6-96231b3b80d8
21 lines
386 B
LLVM
21 lines
386 B
LLVM
;
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; Register constraint "r" shouldn't take long long unless
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; The target is 64 bit.
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;
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;
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; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=n64 < %s | FileCheck %s
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define i32 @main() nounwind {
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entry:
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; r with long long
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;CHECK: #APP
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;CHECK: addiu ${{[0-9]+}},${{[0-9]+}},3
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;CHECK: #NO_APP
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tail call i64 asm sideeffect "addiu $0,$1,$2", "=r,r,i"(i64 7, i64 3) nounwind
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ret i32 0
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}
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