Alex Bradbury 5a3d179fab [RISCV] Initial codegen support for ALU operations ...

This adds the minimum necessary to support codegen for simple ALU operations
on RV32. Prolog and epilog insertion, support for memory operations etc etc 
follow in future patches.

Leave guessInstructionProperties=1 until https://reviews.llvm.org/D37065 is 
reviewed and lands.

Differential Revision: https://reviews.llvm.org/D29933


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316188 91177308-0d34-0410-b5e6-96231b3b80d8

2017-10-19 21:37:38 +00:00

..

alu32.ll

[RISCV] Initial codegen support for ALU operations

2017-10-19 21:37:38 +00:00

lit.local.cfg

[RISCV] Initial codegen support for ALU operations

2017-10-19 21:37:38 +00:00