llvm/test/CodeGen/X86/2011-06-14-PreschedRegalias.ll
Ahmed Bougacha 4c690f3954 [X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr.
This re-applies r268760, reverted in r268794.
Fixes http://llvm.org/PR27670

The original imp-defs assertion was way overzealous: forward all
implicit operands, except imp-defs of the new super-reg def (r268787
for GR64, but also possible for GR16->GR32), or imp-uses of the new
super-reg use.
While there, mark the source use as Undef, and add an imp-use of the
old source reg: that should cover any case of dead super-regs.

At the stage the pass runs, flags are unlikely to matter anyway;
still, let's be as correct as possible.

Also add MIR tests for the various interesting cases.

Original commit message:
Codesize is less (16) or equal (8), and we avoid partial
dependencies.

Differential Revision: http://reviews.llvm.org/D19999

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268831 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-07 01:11:17 +00:00

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460 B
LLVM

; RUN: llc < %s -march=x86-64 -stress-sched | FileCheck %s
; REQUIRES: asserts
; Test interference between physreg aliases during preRAsched.
; mul wants an operand in AL, but call clobbers it.
define i8 @f(i8 %v1, i8 %v2) nounwind {
entry:
; CHECK: callq
; CHECK: movl %{{.*}}, %eax
; CHECK: mulb
; CHECK: mulb
%rval = tail call i8 @bar() nounwind
%m1 = mul i8 %v1, %v2
%m2 = mul i8 %m1, %rval
ret i8 %m2
}
declare i8 @bar()