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87d1190761
If the target allows the alignment, this should be OK. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267217 91177308-0d34-0410-b5e6-96231b3b80d8
139 lines
4.5 KiB
LLVM
139 lines
4.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx | FileCheck %s
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define <8 x float> @A(<8 x float> %a) nounwind uwtable readnone ssp {
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; CHECK-LABEL: A:
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; CHECK: ## BB#0: ## %entry
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; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm0
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; CHECK-NEXT: retq
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entry:
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%shuffle = shufflevector <8 x float> %a, <8 x float> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 8, i32 8, i32 8>
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ret <8 x float> %shuffle
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}
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define <4 x double> @B(<4 x double> %a) nounwind uwtable readnone ssp {
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; CHECK-LABEL: B:
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; CHECK: ## BB#0: ## %entry
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; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm0
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; CHECK-NEXT: retq
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entry:
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%shuffle = shufflevector <4 x double> %a, <4 x double> undef, <4 x i32> <i32 2, i32 3, i32 4, i32 4>
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ret <4 x double> %shuffle
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}
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define void @t0(float* nocapture %addr, <8 x float> %a) nounwind uwtable ssp {
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; CHECK-LABEL: t0:
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; CHECK: ## BB#0: ## %entry
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; CHECK-NEXT: vextractf128 $1, %ymm0, (%rdi)
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; CHECK-NEXT: vzeroupper
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; CHECK-NEXT: retq
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entry:
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%0 = tail call <4 x float> @llvm.x86.avx.vextractf128.ps.256(<8 x float> %a, i8 1)
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%1 = bitcast float* %addr to <4 x float>*
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store <4 x float> %0, <4 x float>* %1, align 16
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ret void
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}
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define void @t2(double* nocapture %addr, <4 x double> %a) nounwind uwtable ssp {
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; CHECK-LABEL: t2:
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; CHECK: ## BB#0: ## %entry
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; CHECK-NEXT: vextractf128 $1, %ymm0, (%rdi)
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; CHECK-NEXT: vzeroupper
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; CHECK-NEXT: retq
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entry:
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%0 = tail call <2 x double> @llvm.x86.avx.vextractf128.pd.256(<4 x double> %a, i8 1)
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%1 = bitcast double* %addr to <2 x double>*
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store <2 x double> %0, <2 x double>* %1, align 16
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ret void
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}
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define void @t4(<2 x i64>* nocapture %addr, <4 x i64> %a) nounwind uwtable ssp {
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; CHECK-LABEL: t4:
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; CHECK: ## BB#0: ## %entry
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; CHECK-NEXT: vextractf128 $1, %ymm0, (%rdi)
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; CHECK-NEXT: vzeroupper
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; CHECK-NEXT: retq
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entry:
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%0 = bitcast <4 x i64> %a to <8 x i32>
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%1 = tail call <4 x i32> @llvm.x86.avx.vextractf128.si.256(<8 x i32> %0, i8 1)
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%2 = bitcast <4 x i32> %1 to <2 x i64>
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store <2 x i64> %2, <2 x i64>* %addr, align 16
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ret void
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}
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define void @t5(float* nocapture %addr, <8 x float> %a) nounwind uwtable ssp {
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; CHECK-LABEL: t5:
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; CHECK: ## BB#0: ## %entry
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; CHECK-NEXT: vmovaps %xmm0, (%rdi)
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; CHECK-NEXT: vzeroupper
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; CHECK-NEXT: retq
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entry:
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%0 = tail call <4 x float> @llvm.x86.avx.vextractf128.ps.256(<8 x float> %a, i8 0)
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%1 = bitcast float* %addr to <4 x float>*
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store <4 x float> %0, <4 x float>* %1, align 16
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ret void
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}
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define void @t6(double* nocapture %addr, <4 x double> %a) nounwind uwtable ssp {
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; CHECK-LABEL: t6:
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; CHECK: ## BB#0: ## %entry
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; CHECK-NEXT: vmovaps %xmm0, (%rdi)
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; CHECK-NEXT: vzeroupper
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; CHECK-NEXT: retq
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entry:
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%0 = tail call <2 x double> @llvm.x86.avx.vextractf128.pd.256(<4 x double> %a, i8 0)
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%1 = bitcast double* %addr to <2 x double>*
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store <2 x double> %0, <2 x double>* %1, align 16
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ret void
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}
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define void @t7(<2 x i64>* nocapture %addr, <4 x i64> %a) nounwind uwtable ssp {
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; CHECK-LABEL: t7:
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; CHECK: ## BB#0: ## %entry
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; CHECK-NEXT: vmovaps %xmm0, (%rdi)
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; CHECK-NEXT: vzeroupper
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; CHECK-NEXT: retq
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entry:
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%0 = bitcast <4 x i64> %a to <8 x i32>
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%1 = tail call <4 x i32> @llvm.x86.avx.vextractf128.si.256(<8 x i32> %0, i8 0)
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%2 = bitcast <4 x i32> %1 to <2 x i64>
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store <2 x i64> %2, <2 x i64>* %addr, align 16
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ret void
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}
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define void @t8(<2 x i64>* nocapture %addr, <4 x i64> %a) nounwind uwtable ssp {
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; CHECK-LABEL: t8:
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; CHECK: ## BB#0: ## %entry
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; CHECK-NEXT: vmovups %xmm0, (%rdi)
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; CHECK-NEXT: vzeroupper
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; CHECK-NEXT: retq
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entry:
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%0 = bitcast <4 x i64> %a to <8 x i32>
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%1 = tail call <4 x i32> @llvm.x86.avx.vextractf128.si.256(<8 x i32> %0, i8 0)
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%2 = bitcast <4 x i32> %1 to <2 x i64>
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store <2 x i64> %2, <2 x i64>* %addr, align 1
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ret void
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}
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; PR15462
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define void @t9(i64* %p) {
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; CHECK-LABEL: t9:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vxorps %ymm0, %ymm0, %ymm0
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; CHECK-NEXT: vmovups %ymm0, (%rdi)
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; CHECK-NEXT: vzeroupper
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; CHECK-NEXT: retq
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store i64 0, i64* %p
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%q = getelementptr i64, i64* %p, i64 1
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store i64 0, i64* %q
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%r = getelementptr i64, i64* %p, i64 2
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store i64 0, i64* %r
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%s = getelementptr i64, i64* %p, i64 3
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store i64 0, i64* %s
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ret void
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}
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declare <2 x double> @llvm.x86.avx.vextractf128.pd.256(<4 x double>, i8) nounwind readnone
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declare <4 x float> @llvm.x86.avx.vextractf128.ps.256(<8 x float>, i8) nounwind readnone
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declare <4 x i32> @llvm.x86.avx.vextractf128.si.256(<8 x i32>, i8) nounwind readnone
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