llvm/test/CodeGen/X86/misched-aa-mmos.ll
David Blaikie 7c9c6ed761 [opaque pointer type] Add textual IR support for explicit type parameter to load instruction
Essentially the same as the GEP change in r230786.

A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)

import fileinput
import sys
import re

pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")

for line in sys.stdin:
  sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))

Reviewers: rafael, dexonsmith, grosser

Differential Revision: http://reviews.llvm.org/D7649

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-27 21:17:42 +00:00

38 lines
1.1 KiB
LLVM

; RUN: llc -enable-misched -enable-aa-sched-mi < %s
; This generates a decw instruction, which has two MMOs, and an alias SU edge
; query involving that instruction. Make sure this does not crash.
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"
%s1 = type { i16, i16, i32 }
%c1 = type { %s1*, %u1, i16, i8 }
%u1 = type { i64 }
declare zeroext i1 @bar(i64*, i32) #5
define i32 @foo() #0 align 2 {
entry:
%temp_rhs = alloca %c1, align 8
br i1 undef, label %if.else56, label %cond.end.i
cond.end.i:
%significand.i18.i = getelementptr inbounds %c1, %c1* %temp_rhs, i64 0, i32 1
%exponent.i = getelementptr inbounds %c1, %c1* %temp_rhs, i64 0, i32 2
%0 = load i16, i16* %exponent.i, align 8
%sub.i = add i16 %0, -1
store i16 %sub.i, i16* %exponent.i, align 8
%parts.i.i = bitcast %u1* %significand.i18.i to i64**
%1 = load i64*, i64** %parts.i.i, align 8
%call5.i = call zeroext i1 @bar(i64* %1, i32 undef) #1
unreachable
if.else56:
unreachable
}
attributes #0 = { nounwind uwtable }
attributes #1 = { nounwind }