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41c48e040d
changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268954 91177308-0d34-0410-b5e6-96231b3b80d8
201 lines
5.2 KiB
LLVM
201 lines
5.2 KiB
LLVM
; RUN: llc -mtriple=i386-linux-gnu %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK32
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; RUN: llc -mtriple=x86_64-linux-gnu -mattr=+sahf %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK64
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; TODO: Reenable verify-machineinstrs once the if (!AXDead) // FIXME in
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; X86InstrInfo::copyPhysReg() is resolved.
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; The peephole optimizer can elide some physical register copies such as
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; EFLAGS. Make sure the flags are used directly, instead of needlessly using
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; lahf, when possible.
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@L = external global i32
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@M = external global i8
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declare i32 @bar(i64)
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; CHECK-LABEL: plus_one
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; CHECK-NOT: seto
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; CHECK-NOT: lahf
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; CHECK-NOT: sahf
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; CHECK-NOT: pushf
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; CHECK-NOT: popf
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; CHECK: incl L
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define i1 @plus_one() {
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entry:
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%loaded_L = load i32, i32* @L
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%val = add nsw i32 %loaded_L, 1 ; N.B. will emit inc.
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store i32 %val, i32* @L
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%loaded_M = load i8, i8* @M
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%masked = and i8 %loaded_M, 8
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%M_is_true = icmp ne i8 %masked, 0
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%L_is_false = icmp eq i32 %val, 0
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%cond = and i1 %L_is_false, %M_is_true
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br i1 %cond, label %exit2, label %exit
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exit:
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ret i1 true
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exit2:
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ret i1 false
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}
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; CHECK-LABEL: plus_forty_two
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; CHECK-NOT: seto
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; CHECK-NOT: lahf
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; CHECK-NOT: sahf
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; CHECK-NOT: pushf
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; CHECK-NOT: popf
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; CHECK: addl $42,
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define i1 @plus_forty_two() {
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entry:
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%loaded_L = load i32, i32* @L
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%val = add nsw i32 %loaded_L, 42 ; N.B. won't emit inc.
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store i32 %val, i32* @L
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%loaded_M = load i8, i8* @M
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%masked = and i8 %loaded_M, 8
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%M_is_true = icmp ne i8 %masked, 0
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%L_is_false = icmp eq i32 %val, 0
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%cond = and i1 %L_is_false, %M_is_true
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br i1 %cond, label %exit2, label %exit
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exit:
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ret i1 true
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exit2:
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ret i1 false
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}
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; CHECK-LABEL: minus_one
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; CHECK-NOT: seto
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; CHECK-NOT: lahf
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; CHECK-NOT: sahf
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; CHECK-NOT: pushf
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; CHECK-NOT: popf
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; CHECK: decl L
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define i1 @minus_one() {
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entry:
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%loaded_L = load i32, i32* @L
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%val = add nsw i32 %loaded_L, -1 ; N.B. will emit dec.
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store i32 %val, i32* @L
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%loaded_M = load i8, i8* @M
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%masked = and i8 %loaded_M, 8
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%M_is_true = icmp ne i8 %masked, 0
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%L_is_false = icmp eq i32 %val, 0
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%cond = and i1 %L_is_false, %M_is_true
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br i1 %cond, label %exit2, label %exit
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exit:
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ret i1 true
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exit2:
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ret i1 false
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}
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; CHECK-LABEL: minus_forty_two
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; CHECK-NOT: seto
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; CHECK-NOT: lahf
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; CHECK-NOT: sahf
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; CHECK-NOT: pushf
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; CHECK-NOT: popf
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; CHECK: addl $-42,
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define i1 @minus_forty_two() {
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entry:
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%loaded_L = load i32, i32* @L
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%val = add nsw i32 %loaded_L, -42 ; N.B. won't emit dec.
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store i32 %val, i32* @L
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%loaded_M = load i8, i8* @M
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%masked = and i8 %loaded_M, 8
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%M_is_true = icmp ne i8 %masked, 0
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%L_is_false = icmp eq i32 %val, 0
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%cond = and i1 %L_is_false, %M_is_true
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br i1 %cond, label %exit2, label %exit
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exit:
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ret i1 true
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exit2:
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ret i1 false
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}
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; CHECK-LABEL: test_intervening_call:
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; CHECK: cmpxchg
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; CHECK: seto %al
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; CHECK-NEXT: lahf
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; CHECK: call{{[lq]}} bar
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; CHECK: addb $127, %al
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; CHECK-NEXT: sahf
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define i64 @test_intervening_call(i64* %foo, i64 %bar, i64 %baz) {
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; cmpxchg sets EFLAGS, call clobbers it, then br uses EFLAGS.
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%cx = cmpxchg i64* %foo, i64 %bar, i64 %baz seq_cst seq_cst
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%v = extractvalue { i64, i1 } %cx, 0
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%p = extractvalue { i64, i1 } %cx, 1
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call i32 @bar(i64 %v)
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br i1 %p, label %t, label %f
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t:
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ret i64 42
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f:
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ret i64 0
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}
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; CHECK-LABEL: test_two_live_flags:
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; CHECK: cmpxchg
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; CHECK: seto %al
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; CHECK-NEXT: lahf
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; Save result of the first cmpxchg into a temporary.
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; For 32-bit ISA, EDX, EAX are used by the results.
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; EAX, EBX, ECX, and EDX are used to set the arguments.
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; That leaves us EDI and ESI.
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; CHECK32-NEXT: movl %[[AX:eax]], %[[TMP:e[ds]i]]
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; For 64-bit ISA, RAX is used for both the result and argument.
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; This leaves us plenty of choices for the temporary. For now,
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; this is rdx, but any register could do.
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; CHECK64-NEXT: mov{{[lq]}} %[[AX:[er]ax]], %[[TMP:rdx]]
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; CHECK: cmpxchg
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; CHECK-NEXT: sete %al
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; Save result of the second cmpxchg onto the stack.
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; CHECK-NEXT: push{{[lq]}} %[[AX]]
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; Restore result of the first cmpxchg from D, put it back in EFLAGS.
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; CHECK-NEXT: mov{{[lq]}} %[[TMP]], %[[AX]]
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; CHECK-NEXT: addb $127, %al
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; CHECK-NEXT: sahf
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; Restore result of the second cmpxchg from the stack.
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; CHECK-NEXT: pop{{[lq]}} %[[AX]]
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; Test from EFLAGS restored from first cmpxchg, jump if that fails.
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; CHECK-NEXT: jne
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; Fallthrough to test the second cmpxchg's result.
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; CHECK: testb %al, %al
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; CHECK-NEXT: je
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define i64 @test_two_live_flags(
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i64* %foo0, i64 %bar0, i64 %baz0,
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i64* %foo1, i64 %bar1, i64 %baz1) {
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%cx0 = cmpxchg i64* %foo0, i64 %bar0, i64 %baz0 seq_cst seq_cst
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%p0 = extractvalue { i64, i1 } %cx0, 1
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%cx1 = cmpxchg i64* %foo1, i64 %bar1, i64 %baz1 seq_cst seq_cst
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%p1 = extractvalue { i64, i1 } %cx1, 1
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%flag = and i1 %p0, %p1
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br i1 %flag, label %t, label %f
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t:
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ret i64 42
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f:
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ret i64 0
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}
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; CHECK-LABEL: asm_clobbering_flags:
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; CHECK: test
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; CHECK-NEXT: setg
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; CHECK-NEXT: #APP
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; CHECK-NEXT: bsfl
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: movl
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; CHECK-NEXT: ret
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define i1 @asm_clobbering_flags(i32* %mem) {
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%val = load i32, i32* %mem, align 4
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%cmp = icmp sgt i32 %val, 0
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%res = tail call i32 asm "bsfl $1,$0", "=r,r,~{cc},~{dirflag},~{fpsr},~{flags}"(i32 %val)
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store i32 %res, i32* %mem, align 4
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ret i1 %cmp
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}
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