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6c67e89b60
i1 is now a legal type for X86 with AVX512. There were some paths in X86FastISel which were not quite ready to see an i1 value: they were not quite sure how to deal with sign/zero extends for call arguments. DTRT by extending to i8 for zeroext and bailing out of FastISel for signext. This fixes PR27591. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268470 91177308-0d34-0410-b5e6-96231b3b80d8
43 lines
1.0 KiB
LLVM
43 lines
1.0 KiB
LLVM
; RUN: llc -o - -O0 < %s | FileCheck %s
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-linux-gnu"
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define void @test1(i32 %x) #0 {
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entry:
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%tobool = icmp ne i32 %x, 0
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call void @callee1(i1 zeroext %tobool)
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ret void
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}
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; CHECK-LABEL: test1:
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; CHECK: cmpl $0, %edi
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; CHECK-NEXT: setne %al
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; CHECK-NEXT: andb $1, %al
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; CHECK-NEXT: movzbl %al, %edi
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; CHECK-NEXT: callq callee1
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define void @test2(i32 %x) #0 {
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entry:
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%tobool = icmp ne i32 %x, 0
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call void @callee2(i1 signext %tobool)
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ret void
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}
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; CHECK-LABEL: test2:
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; CHECK: cmpl $0, %edi
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; CHECK-NEXT: setne %al
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; CHECK-NEXT: kmovb %eax, %k0
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; CHECK-NEXT: kmovw %k0, %edi
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; CHECK-NEXT: andl $1, %edi
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; CHECK-NEXT: movb %dil, %al
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; CHECK-NEXT: xorl %edi, %edi
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; CHECK-NEXT: testb %al, %al
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; CHECK-NEXT: movl $-1, %ecx
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; CHECK-NEXT: cmovnel %ecx, %edi
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; CHECK-NEXT: callq callee2
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declare void @callee1(i1 zeroext)
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declare void @callee2(i1 signext)
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attributes #0 = { nounwind "target-cpu"="skylake-avx512" }
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