llvm/test/CodeGen/X86/shift-coalesce.ll
David Blaikie 7c9c6ed761 [opaque pointer type] Add textual IR support for explicit type parameter to load instruction
Essentially the same as the GEP change in r230786.

A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)

import fileinput
import sys
import re

pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")

for line in sys.stdin:
  sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))

Reviewers: rafael, dexonsmith, grosser

Differential Revision: http://reviews.llvm.org/D7649

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-27 21:17:42 +00:00

16 lines
509 B
LLVM

; RUN: llc < %s -march=x86 -x86-asm-syntax=intel | \
; RUN: grep "shld.*cl"
; RUN: llc < %s -march=x86 -x86-asm-syntax=intel | \
; RUN: not grep "mov cl, bl"
; PR687
define i64 @foo(i64 %x, i64* %X) {
%tmp.1 = load i64, i64* %X ; <i64> [#uses=1]
%tmp.3 = trunc i64 %tmp.1 to i8 ; <i8> [#uses=1]
%shift.upgrd.1 = zext i8 %tmp.3 to i64 ; <i64> [#uses=1]
%tmp.4 = shl i64 %x, %shift.upgrd.1 ; <i64> [#uses=1]
ret i64 %tmp.4
}