llvm/test/CodeGen/X86/switch-or.ll
Benjamin Kramer c9f2b5d535 [SDAG switch lowering] Fix switch case -> or merging for 0 and INT_MIN
The big/small ordering here is based on signed values so SmallValue will
be INT_MIN and BigValue 0. This shouldn't be a problem but the code
assumed that BigValue always had more bits set than SmallValue.

We used to just miss the transformation, but a recent refactoring of
mine turned this into an assertion failure.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239105 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-04 22:05:51 +00:00

42 lines
782 B
LLVM

; RUN: llc -march=x86 -asm-verbose=false < %s | FileCheck %s
; Check that merging switch cases that differ in one bit works.
; CHECK-LABEL: test1
; CHECK: orl $2
; CHECK-NEXT: cmpl $6
define void @test1(i32 %variable) nounwind {
entry:
switch i32 %variable, label %if.end [
i32 4, label %if.then
i32 6, label %if.then
]
if.then:
%call = tail call i32 (...) @bar() nounwind
ret void
if.end:
ret void
}
; CHECK-LABEL: test2
; CHECK: orl $-2147483648
; CHECK-NEXT: cmpl $-2147483648
define void @test2(i32 %variable) nounwind {
entry:
switch i32 %variable, label %if.end [
i32 0, label %if.then
i32 -2147483648, label %if.then
]
if.then:
%call = tail call i32 (...) @bar() nounwind
ret void
if.end:
ret void
}
declare i32 @bar(...) nounwind