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184f8f7c10
TableGen had been nicely generating code to print a number of instructions using shorter aliases (and PowerPC has plenty of short mnemonics), but we were not calling it. For some of the aliases we support in the parser, TableGen can't infer the "inverse" alias relationship, so there is still more to do. Thus, after some hours of updating test cases... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235616 91177308-0d34-0410-b5e6-96231b3b80d8
46 lines
1.4 KiB
LLVM
46 lines
1.4 KiB
LLVM
; RUN: llc < %s -mcpu=pwr8 | FileCheck %s
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; Generated from following C code:
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;
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; void foo (int result, char *addr) {
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; __asm__ __volatile__ (
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; "ld%U1%X1 %0,%1\n"
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; "cmpw %0,%0\n"
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; "bne- 1f\n"
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; "1: isync\n"
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; : "=r" (result)
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; : "m"(*addr) : "memory", "cr0");
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; }
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target datalayout = "e-m:e-i64:64-n32:64"
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target triple = "powerpc64le-unknown-linux-gnu"
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; Function Attrs: nounwind
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; Check that we accept 'U' and 'X' constraints.
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define void @foo(i32 signext %result, i8* %addr) #0 {
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entry:
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%result.addr = alloca i32, align 4
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%addr.addr = alloca i8*, align 8
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store i32 %result, i32* %result.addr, align 4
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store i8* %addr, i8** %addr.addr, align 8
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%0 = load i8*, i8** %addr.addr, align 8
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%1 = call i32 asm sideeffect "ld${1:U}${1:X} $0,$1\0Acmpw $0,$0\0Abne- 1f\0A1: isync\0A", "=r,*m,~{memory},~{cr0}"(i8* %0) #1, !srcloc !1
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store i32 %1, i32* %result.addr, align 4
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ret void
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}
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; CHECK-LABEL: @foo
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; CHECK: ld [[REG:[0-9]+]], 0(4)
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; CHECK: cmpw [[REG]], [[REG]]
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; CHECK: bne- 0, .Ltmp[[TMP:[0-9]+]]
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; CHECK: .Ltmp[[TMP]]:
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; CHECK: isync
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attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
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attributes #1 = { nounwind }
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!llvm.ident = !{!0}
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!0 = !{!"clang version 3.6.0 (trunk 217557)"}
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!1 = !{i32 67, i32 91, i32 110, i32 126}
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