Thomas Lively 16a4c18a23 [WebAssembly] v8x16.shuffle ...

Summary:
Since the shuffle mask is not exposed as an operand in the native ISel
DAG, create a new WebAssembly ISD node exposing the mask. The mask is
lowered as sixteen immediate byte indices no matter what type the
original vector shuffle was operating on.

This CL depends on D51656

Reviewers: aheejin, dschuff

Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D51659

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341718 91177308-0d34-0410-b5e6-96231b3b80d8

2018-09-07 21:54:46 +00:00

..

AArch64

[AArch64] Support reserving x1-7 registers.

2018-09-07 20:58:57 +00:00

AMDGPU

[AMDGPU] Preliminary patch for divergence driven instruction selection. Fold immediate SMRD offset.

2018-09-07 09:05:34 +00:00

ARC

[ARC] Add ARC backend.

2017-08-24 15:40:33 +00:00

ARM

ARM: fix Thumb2 CodeGen for ldrex with folded frame-index.

2018-09-07 09:21:25 +00:00

AVR

[AVR] Redefine the 'LSL' instruction as an alias of 'ADD'

2018-09-01 12:23:00 +00:00

BPF

bpf: add missing RegState to notify MachineInstr verifier necessary register usage

2018-07-27 16:58:52 +00:00

Generic

[DWARF] Unclamp line table version on Darwin for v5 and later.

2018-08-08 21:16:50 +00:00

Hexagon

Add support for getRegisterByName.

2018-09-07 13:36:21 +00:00

Inputs

…

Lanai

Remove SETCCE use from Lanai's backend

2018-06-03 12:56:24 +00:00

Mips

[mips] Disable the selection of mixed microMIPS/MIPS code

2018-09-03 20:48:55 +00:00

MIR

[NFC] - in preparation for adding nsw, nuw and exact as flags to MI

2018-09-06 17:07:29 +00:00

MSP430

[DAGCombiner] Add X / X -> 1 & X % X -> 0 folds (test tweaks)

2018-08-29 11:18:14 +00:00

Nios2

[Nios2] Arithmetic instructions for R1 and R2 ISA.

2018-01-09 11:15:08 +00:00

NVPTX

[NVPTX] Implement isLegalToVectorizeLoadChain

2018-08-27 17:29:43 +00:00

PowerPC

[PowerPC] Combine ADD to ADDZE

2018-09-07 07:56:05 +00:00

RISCV

[RISCV] atomic_store_nn have a different layout to regular store

2018-08-27 07:08:18 +00:00

SPARC

[Sparc] Use ANDN instead of AND if constant can be encoded more efficiently

2018-08-30 14:05:26 +00:00

SystemZ

[DAGCombiner] Add X / X -> 1 & X % X -> 0 folds (test tweaks)

2018-08-29 11:18:14 +00:00

Thumb

CodeGen: Make computeRegisterLiveness search forward first

2018-08-30 07:18:10 +00:00

Thumb2

[SelectionDAG] Improve the legalisation lowering of UMULO.

2018-08-16 18:39:39 +00:00

WebAssembly

[WebAssembly] v8x16.shuffle

2018-09-07 21:54:46 +00:00

WinCFGuard

Rename the cfguard module flag to cfguardtable

2018-08-10 09:48:53 +00:00

WinEH

[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.

2018-05-09 02:40:45 +00:00

X86

[X86] Add codegen tests for narrow PADDUS/PSUBUS patterns for PR38691.

2018-09-07 21:28:46 +00:00

XCore

[DAGCombiner] extend(ifpositive(X)) -> shift-right (not X)

2018-07-15 16:27:07 +00:00