llvm/lib/Target/SparcV9
Nate Begeman 6510b22cec Support multiple ValueTypes per RegisterClass, needed for upcoming vector
work.  This change has no effect on generated code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24563 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-01 04:51:06 +00:00
..
InstrSched
LiveVar
ModuloScheduling
RegAlloc
.cvsignore
DecomposeMultiDimRefs.cpp
EmitBytecodeToAssembly.cpp
InternalGlobalMapper.cpp
MachineCodeForInstruction.cpp
MachineCodeForInstruction.h
MachineFunctionInfo.cpp
MachineFunctionInfo.h
MachineInstrAnnot.h
Makefile
MappingInfo.cpp
MappingInfo.h
SparcV9_F2.td
SparcV9_F3.td
SparcV9_F4.td
SparcV9.burg.in
SparcV9.td
SparcV9AsmPrinter.cpp
SparcV9BurgISel.cpp
SparcV9BurgISel.h
SparcV9CodeEmitter.cpp
SparcV9CodeEmitter.h
SparcV9FrameInfo.cpp
SparcV9FrameInfo.h
SparcV9Instr.def
SparcV9InstrForest.h
SparcV9InstrInfo.h
SparcV9InstrInfo.td
SparcV9Internals.h
SparcV9JITInfo.cpp
SparcV9JITInfo.h
SparcV9PeepholeOpts.cpp
SparcV9PreSelection.cpp
SparcV9PrologEpilogInserter.cpp
SparcV9RegClassInfo.cpp
SparcV9RegClassInfo.h
SparcV9RegInfo.cpp
SparcV9RegInfo.h
SparcV9RegisterInfo.cpp
SparcV9RegisterInfo.h
SparcV9RegisterInfo.td
SparcV9Relocations.h
SparcV9SchedInfo.cpp
SparcV9StackSlots.cpp
SparcV9TargetMachine.cpp
SparcV9TargetMachine.h
SparcV9TmpInstr.cpp
SparcV9TmpInstr.h