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https://github.com/RPCS3/llvm.git
synced 2026-08-26 18:26:51 -04:00
Craig Topper
9cb26abb0f
These instructions perform the same operation, but the semantic of which operand is destroyed is reversed. If the same register is used as both operands we can change the execution domain without worrying about this difference. Unfortunately, this really only works in cases where the input register is killed by the instruction. If its not killed, the two address isntruction pass inserts a copy that will become a move instruction. This makes the instruction use different physical registers that contain the same data at the time the unpck/movhlps executes. I've considered using a unary pseudo instruction with tied operand to trick the two address instruction pass. We could then expand the pseudo post regalloc to get the same physical register on both inputs. Differential Revision: https://reviews.llvm.org/D50157 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338735 91177308-0d34-0410-b5e6-96231b3b80d8
105 lines
3.1 KiB
LLVM
105 lines
3.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown-linux-gnu -mattr=+sse2,-sse4.1 | FileCheck %s --check-prefix=X32
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; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+sse2,-sse4.1 | FileCheck %s --check-prefix=X64
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define void @test1(<4 x float>* %F, float* %f) nounwind {
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; X32-LABEL: test1:
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; X32: # %bb.0: # %entry
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X32-NEXT: movaps (%ecx), %xmm0
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; X32-NEXT: addps %xmm0, %xmm0
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; X32-NEXT: movss %xmm0, (%eax)
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; X32-NEXT: retl
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;
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; X64-LABEL: test1:
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; X64: # %bb.0: # %entry
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; X64-NEXT: movaps (%rdi), %xmm0
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; X64-NEXT: addps %xmm0, %xmm0
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; X64-NEXT: movss %xmm0, (%rsi)
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; X64-NEXT: retq
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entry:
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%tmp = load <4 x float>, <4 x float>* %F
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%tmp7 = fadd <4 x float> %tmp, %tmp
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%tmp2 = extractelement <4 x float> %tmp7, i32 0
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store float %tmp2, float* %f
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ret void
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}
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define float @test2(<4 x float>* %F, float* %f) nounwind {
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; X32-LABEL: test2:
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; X32: # %bb.0: # %entry
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; X32-NEXT: pushl %eax
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: movaps (%eax), %xmm0
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; X32-NEXT: addps %xmm0, %xmm0
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; X32-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
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; X32-NEXT: movss %xmm0, (%esp)
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; X32-NEXT: flds (%esp)
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; X32-NEXT: popl %eax
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; X32-NEXT: retl
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;
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; X64-LABEL: test2:
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; X64: # %bb.0: # %entry
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; X64-NEXT: movaps (%rdi), %xmm0
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; X64-NEXT: addps %xmm0, %xmm0
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; X64-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
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; X64-NEXT: retq
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entry:
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%tmp = load <4 x float>, <4 x float>* %F
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%tmp7 = fadd <4 x float> %tmp, %tmp
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%tmp2 = extractelement <4 x float> %tmp7, i32 2
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ret float %tmp2
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}
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define void @test3(float* %R, <4 x float>* %P1) nounwind {
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; X32-LABEL: test3:
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; X32: # %bb.0: # %entry
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X32-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; X32-NEXT: movss %xmm0, (%eax)
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; X32-NEXT: retl
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;
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; X64-LABEL: test3:
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; X64: # %bb.0: # %entry
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; X64-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; X64-NEXT: movss %xmm0, (%rdi)
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; X64-NEXT: retq
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entry:
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%X = load <4 x float>, <4 x float>* %P1
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%tmp = extractelement <4 x float> %X, i32 3
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store float %tmp, float* %R
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ret void
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}
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define double @test4(double %A) nounwind {
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; X32-LABEL: test4:
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; X32: # %bb.0: # %entry
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; X32-NEXT: subl $12, %esp
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; X32-NEXT: calll foo
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; X32-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1,1]
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; X32-NEXT: addsd {{[0-9]+}}(%esp), %xmm0
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; X32-NEXT: movsd %xmm0, (%esp)
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; X32-NEXT: fldl (%esp)
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; X32-NEXT: addl $12, %esp
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; X32-NEXT: retl
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;
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; X64-LABEL: test4:
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; X64: # %bb.0: # %entry
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; X64-NEXT: pushq %rax
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; X64-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill
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; X64-NEXT: callq foo
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; X64-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1,1]
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; X64-NEXT: addsd (%rsp), %xmm0 # 8-byte Folded Reload
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; X64-NEXT: popq %rax
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; X64-NEXT: retq
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entry:
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%tmp1 = call <2 x double> @foo( )
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%tmp2 = extractelement <2 x double> %tmp1, i32 1
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%tmp3 = fadd double %tmp2, %A
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ret double %tmp3
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}
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declare <2 x double> @foo()
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