Alexander Timofeev 6a29119c95 [AMDGPU] Divergence driven ISel. Assign register class for cross block values according to the divergence. ...

Details: To make instruction selection really divergence driven it is necessary to assign
         the correct register classes to the cross block values beforehand. For the divergent targets
         same value type requires different register classes dependent on the value divergence.

Reviewers: rampitec, nhaehnle

Differential Revision: https://reviews.llvm.org/D59990

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361644 91177308-0d34-0410-b5e6-96231b3b80d8

2019-05-24 15:32:18 +00:00

..

AArch64

GlobalISel: support swifterror attribute on AArch64.

2019-05-24 08:40:13 +00:00

AMDGPU

[AMDGPU] Divergence driven ISel. Assign register class for cross block values according to the divergence.

2019-05-24 15:32:18 +00:00

ARC

[ARC] Add ARCOptAddrMode pass to generate postincrement loads/stores.

2019-03-20 20:06:21 +00:00

ARM

[ARM][CGP] Clear SafeWrap before each search

2019-05-23 07:46:39 +00:00

AVR

Add TargetLoweringInfo hook for explicitly setting the ABI calling convention endianess

2019-05-21 06:38:02 +00:00

BPF

[BPF] emit BTF sections only if debuginfo available

2019-05-13 05:00:23 +00:00

Generic

[IR] allow fast-math-flags on select of FP values

2019-05-22 15:50:46 +00:00

Hexagon

[llvm-readobj] Change -long-option to --long-option in tests. NFC

2019-05-01 05:27:20 +00:00

Inputs

…

Lanai

[AsmPrinter] refactor to support %c w/ GlobalAddress'

2019-04-26 18:45:04 +00:00

Mips

[mips] Always check that shift and add optimization is efficient.

2019-05-24 08:39:40 +00:00

MIR

[AMDGPU] gfx1010 tests. NFC.

2019-05-13 19:30:06 +00:00

MSP430

[AsmPrinter] refactor to support %c w/ GlobalAddress'

2019-04-26 18:45:04 +00:00

NVPTX

SelectionDAG: accommodate atomic floating stores.

2019-05-10 11:23:04 +00:00

PowerPC

[PowerPC] Remove CRBits Copy Of Unset/set CBit

2019-05-24 12:05:37 +00:00

RISCV

[RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV

2019-05-23 12:43:13 +00:00

SPARC

[TargetLowering] Extend bool args to inline-asm according to getBooleanType

2019-05-22 16:16:15 +00:00

SystemZ

[TargetLowering] Extend bool args to inline-asm according to getBooleanType

2019-05-22 16:16:15 +00:00

Thumb

[TargetLowering] Extend bool args to inline-asm according to getBooleanType

2019-05-22 16:16:15 +00:00

Thumb2

[TargetLowering] Extend bool args to inline-asm according to getBooleanType

2019-05-22 16:16:15 +00:00

WebAssembly

[WebAssembly] Expand more SIMD float ops

2019-05-24 00:15:04 +00:00

WinCFGuard

[COFF] Emit @feat.00 on 64-bit and set the CFG bit when emitting guardcf tables

2018-09-19 09:58:30 +00:00

WinEH

Fix invalid target triples in tests. (NFC)

2019-03-04 23:37:41 +00:00

X86

[SelectionDAG] computeKnownBits - support constant pool values from target

2019-05-24 10:03:11 +00:00

XCore

[AsmPrinter] refactor to support %c w/ GlobalAddress'

2019-04-26 18:45:04 +00:00