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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73661 91177308-0d34-0410-b5e6-96231b3b80d8
209 lines
8.4 KiB
TableGen
209 lines
8.4 KiB
TableGen
//===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the Thumb2 instruction set.
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//
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//===----------------------------------------------------------------------===//
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// Shifted operands. No register controlled shifts for Thumb2.
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// Note: We do not support rrx shifted operands yet.
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def t2_so_reg : Operand<i32>, // reg imm
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ComplexPattern<i32, 2, "SelectShifterOperand",
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[shl,srl,sra,rotr]> {
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let PrintMethod = "printSOOperand";
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let MIOperandInfo = (ops GPR, i32imm);
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}
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def LO16 : SDNodeXForm<imm, [{
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// Transformation function: shift the immediate value down into the low bits.
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return getI32Imm((unsigned short)N->getZExtValue());
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}]>;
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def HI16 : SDNodeXForm<imm, [{
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// Transformation function: shift the immediate value down into the low bits.
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return getI32Imm((unsigned)N->getZExtValue() >> 16);
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}]>;
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def imm16high : PatLeaf<(i32 imm), [{
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// Returns true if all bits out of the [31..16] range are 0.
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return ((N->getZExtValue() & 0xFFFF0000ULL) == N->getZExtValue());
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}], HI16>;
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def imm16high0xffff : PatLeaf<(i32 imm), [{
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// Returns true if lo 16 bits are set and this is a 32-bit value.
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return ((N->getZExtValue() & 0x0000FFFFULL) == 0xFFFFULL);
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}], HI16>;
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def imm0_4095 : PatLeaf<(i32 imm), [{
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return (uint32_t)N->getZExtValue() < 4096;
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}]>;
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def imm0_4095_neg : PatLeaf<(i32 imm), [{
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return (uint32_t)-N->getZExtValue() < 4096;
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}], imm_neg_XFORM>;
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def imm0_65535 : PatLeaf<(i32 imm), [{
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return N->getZExtValue() < 65536;
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}]>;
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// A6.3.2 Modified immediate constants in Thumb instructions (#<const>)
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// FIXME: Move it the the addrmode matcher code.
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def t2_so_imm : PatLeaf<(i32 imm), [{
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uint64_t v = N->getZExtValue();
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if (v == 0 || v > 0xffffffffUL) return false;
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// variant1 - 0b0000x - 8-bit which could be zero (not supported for now)
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// variant2 - 0b00nnx - 8-bit repeated inside the 32-bit room
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unsigned hi16 = (unsigned)(v >> 16);
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unsigned lo16 = (unsigned)(v & 0xffffUL);
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bool valid = (hi16 == lo16) && (
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(v & 0x00ff00ffUL) == 0 || // type 0001x
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(v & 0xff00ff00UL) == 0 || // type 0010x
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((lo16 >> 8) == (lo16 & 0xff))); // type 0011x
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if (valid) return true;
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// variant3 - 0b01000..0b11111 - 8-bit shifted inside the 32-bit room
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unsigned shift = CountLeadingZeros_32(v);
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uint64_t mask = (0xff000000ULL >> shift);
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// If valid, it is type 01000 + shift
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return ((shift < 24) && (v & mask) > 0) && ((v & (~mask)) == 0);
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}]>;
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//===----------------------------------------------------------------------===//
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// Thumb-2 to cover the functionality of the ARM instruction set.
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//
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/// T2I_bin_irs - Defines a set of (op reg, {so_imm|reg|so_reg}) patterns for a
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// binary operation that produces a value.
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multiclass T2I_bin_irs<string opc, PatFrag opnode> {
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// shifted imm
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def ri : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
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!strconcat(opc, " $dst, $lhs, $rhs"),
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[(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
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Requires<[HasThumb2]>;
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// register
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def rr : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
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!strconcat(opc, " $dst, $lhs, $rhs"),
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[(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>,
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Requires<[HasThumb2]>;
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// shifted register
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def rs : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
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!strconcat(opc, " $dst, $lhs, $rhs"),
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[(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>,
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Requires<[HasThumb2]>;
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}
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/// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
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/// instruction modifies the CPSR register.
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let Defs = [CPSR] in {
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multiclass T2I_bin_s_irs<string opc, PatFrag opnode> {
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// shifted imm
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def ri : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
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!strconcat(opc, "s $dst, $lhs, $rhs"),
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[(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
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Requires<[HasThumb2]>;
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// register
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def rr : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
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!strconcat(opc, "s $dst, $lhs, $rhs"),
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[(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>,
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Requires<[HasThumb2]>;
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// shifted register
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def rs : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
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!strconcat(opc, "s $dst, $lhs, $rhs"),
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[(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>,
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Requires<[HasThumb2]>;
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}
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}
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/// T2I_bin_c_irs - Similar to T2I_bin_irs except it uses the 's' bit. Also the
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/// instruction can optionally set the CPSR register.
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let Uses = [CPSR] in {
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multiclass T2I_bin_c_irs<string opc, PatFrag opnode> {
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// shifted imm
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def ri : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs, cc_out:$s),
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!strconcat(opc, "${s} $dst, $lhs, $rhs"),
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[(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
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Requires<[HasThumb2]>;
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// register
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def rr : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs, cc_out:$s),
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!strconcat(opc, "${s} $dst, $lhs, $rhs"),
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[(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>,
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Requires<[HasThumb2]>;
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// shifted register
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def rs : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs, cc_out:$s),
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!strconcat(opc, "${s} $dst, $lhs, $rhs"),
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[(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>,
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Requires<[HasThumb2]>;
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}
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}
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//===----------------------------------------------------------------------===//
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// Arithmetic Instructions.
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//
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//===----------------------------------------------------------------------===//
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// Move Instructions.
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//
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def tMOVi16 : PseudoInst<(outs GPR:$dst), (ins i32imm:$src),
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"movw $dst, $src",
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[(set GPR:$dst, imm0_65535:$src)]>,
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Requires<[HasThumb2]>;
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let isTwoAddress = 1 in
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def tMOVTi16 : PseudoInst<(outs GPR:$dst), (ins GPR:$src, i32imm:$imm),
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"movt $dst, $imm",
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[(set GPR:$dst, (or (and GPR:$src, 0xffff),
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imm16high:$imm))]>,
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Requires<[HasThumb2]>;
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def : Pat<(and (or GPR:$src, imm16high:$imm1), imm16high0xffff:$imm2),
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(tMOVTi16 GPR:$src, (HI16 imm16high:$imm1))>,
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Requires<[HasThumb2]>;
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def : Pat<(i32 imm:$imm),
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(tMOVTi16 (tMOVi16 (LO16 imm:$imm)),(HI16 imm:$imm))>,
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Requires<[HasThumb2]>;
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//===----------------------------------------------------------------------===//
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// Arithmetic Instructions.
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//
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defm t2ADD : T2I_bin_irs <"add", BinOpFrag<(add node:$LHS, node:$RHS)>>;
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defm t2SUB : T2I_bin_irs <"sub", BinOpFrag<(sub node:$LHS, node:$RHS)>>;
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def tADDri12 : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
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"add $dst, $lhs, $rhs",
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[(set GPR:$dst, (add GPR:$lhs, imm0_4095:$rhs))]>,
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Requires<[HasThumb2]>;
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def tSUBri12 : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
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"sub $dst, $lhs, $rhs",
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[(set GPR:$dst, (add GPR:$lhs, imm0_4095_neg:$rhs))]>,
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Requires<[HasThumb2]>;
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defm t2ADDS : T2I_bin_s_irs<"add", BinOpFrag<(addc node:$LHS, node:$RHS)>>;
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defm t2SUBS : T2I_bin_s_irs<"sub", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
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defm t2ADC : T2I_bin_c_irs<"adc", BinOpFrag<(adde node:$LHS, node:$RHS)>>;
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defm t2SBC : T2I_bin_c_irs<"sbc", BinOpFrag<(sube node:$LHS, node:$RHS)>>;
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def tMLS : PseudoInst<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
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"mls $dst, $a, $b, $c",
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[(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>,
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Requires<[HasThumb2]>;
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def tORNrs : PseudoInst<(outs GPR:$dst), (ins GPR:$src1, t2_so_reg:$src2),
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"orn $dst, $src1, $src2",
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[(set GPR:$dst, (or GPR:$src1, (not t2_so_reg: $src2)))]>,
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Requires<[HasThumb2]>;
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