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https://github.com/RPCS3/llvm.git
synced 2026-07-25 12:46:21 -04:00
Kang Zhang
7cb6f24031
Summary: Fast selection of llvm fptoi & fptrunc instructions is not handled well about VSX instruction support. We'd use VSX float convert integer instruction instead of non-vsx float convert integer instruction if the operand register class is VSSRC or VSFRC because i32 and i64 are mapped to VSSRC and VSFRC correspondingly if VSX feature is openeded. For float trunc instruction, we do this silimar work like float convert integer instruction to try to use VSX instruction. Reviewed By: jsji Differential Revision: https://reviews.llvm.org/D58430 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354762 91177308-0d34-0410-b5e6-96231b3b80d8
28 lines
800 B
LLVM
28 lines
800 B
LLVM
; RUN: llc -mcpu=generic -mtriple=powerpc64le-unknown-unknown -O0 < %s \
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; RUN: -verify-machineinstrs | FileCheck %s --check-prefix=GENERIC
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; RUN: llc -mcpu=ppc -mtriple=powerpc64le-unknown-unknown -O0 < %s \
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; RUN: -verify-machineinstrs | FileCheck %s
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define i32 @bad(double %x) {
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%1 = fptoui double %x to i32
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ret i32 %1
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; CHECK: fctidz [[REG0:[0-9]+]], 1
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; CHECK: stfd [[REG0]], [[OFF:.*]](1)
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; CHECK: lwz {{[0-9]*}}, [[OFF]](1)
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; GENERIC: xscvdpuxws [[REG0:[0-9]+]], 1
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; GENERIC: mfvsrwz {{[0-9]*}}, [[REG0]]
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}
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define i32 @bad1(float %x) {
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entry:
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%0 = fptosi float %x to i32
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ret i32 %0
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; CHECK: fctiwz [[REG0:[0-9]+]], 1
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; CHECK: stfd [[REG0]], [[OFF:.*]](1)
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; CHECK: lwa {{[0-9]*}}, [[OFF]](1)
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; GENERIC: xscvdpsxws [[REG0:[0-9]+]], 1
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; GENERIC: mfvsrwz {{[0-9]*}}, [[REG0]]
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}
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