Benjamin Kramer d54bf7ceef R600: Fix bug detected by GCC warning. ...

R600TextureIntrinsicsReplacer.cpp:232: warning: the address of ‘ArgsType’ will always evaluate as ‘true’

This doesn't have any effect on the output as a vararg intrinsic behaves the
same way as a non-vararg one.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182293 91177308-0d34-0410-b5e6-96231b3b80d8

2013-05-20 15:58:43 +00:00

..

InstPrinter

R600: Improve texture handling

2013-05-17 16:50:20 +00:00

MCTargetDesc

Fix the build in c++11 mode.

2013-05-17 22:45:52 +00:00

TargetInfo

…

AMDGPU.h

R600: Improve texture handling

2013-05-17 16:50:20 +00:00

AMDGPU.td

…

AMDGPUAsmPrinter.cpp

R600: Emit config values in register / value pairs

2013-05-06 17:50:51 +00:00

AMDGPUAsmPrinter.h

R600: Emit used GPRs count

2013-04-17 15:17:25 +00:00

AMDGPUCallingConv.td

…

AMDGPUConvertToISA.cpp

…

AMDGPUFrameLowering.cpp

…

AMDGPUFrameLowering.h

…

AMDGPUIndirectAddressing.cpp

…

AMDGPUInstrInfo.cpp

…

AMDGPUInstrInfo.h

…

AMDGPUInstrInfo.td

R600: Swap the legality of rotl and rotr

2013-05-20 15:02:19 +00:00

AMDGPUInstructions.td

R600: Swap the legality of rotl and rotr

2013-05-20 15:02:19 +00:00

AMDGPUIntrinsics.td

…

AMDGPUISelLowering.cpp

R600: Swap the legality of rotl and rotr

2013-05-20 15:02:19 +00:00

AMDGPUISelLowering.h

R600: Swap the legality of rotl and rotr

2013-05-20 15:02:19 +00:00

AMDGPUMachineFunction.cpp

R600: Initialize AMDGPUMachineFunction::ShaderType to ShaderType::COMPUTE

2013-04-26 18:32:24 +00:00

AMDGPUMachineFunction.h

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AMDGPUMCInstLower.cpp

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AMDGPUMCInstLower.h

…

AMDGPURegisterInfo.cpp

…

AMDGPURegisterInfo.h

…

AMDGPURegisterInfo.td

…

AMDGPUStructurizeCFG.cpp

…

AMDGPUSubtarget.cpp

R600: Factorize Fetch size limit inside AMDGPUSubTarget

2013-05-17 16:49:55 +00:00

AMDGPUSubtarget.h

R600: Factorize Fetch size limit inside AMDGPUSubTarget

2013-05-17 16:49:55 +00:00

AMDGPUTargetMachine.cpp

R600: Improve texture handling

2013-05-17 16:50:20 +00:00

AMDGPUTargetMachine.h

…

AMDIL7XXDevice.cpp

…

AMDIL7XXDevice.h

…

AMDIL.h

…

AMDILBase.td

R600: Add FetchInst bit to instruction defs to denote vertex/tex instructions

2013-04-30 00:13:39 +00:00

AMDILCFGStructurizer.cpp

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AMDILDevice.cpp

…

AMDILDevice.h

…

AMDILDeviceInfo.cpp

R600/SI: Add processor type for Hainan asic

2013-05-14 14:42:56 +00:00

AMDILDeviceInfo.h

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AMDILDevices.h

…

AMDILEvergreenDevice.cpp

…

AMDILEvergreenDevice.h

…

AMDILInstrInfo.td

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AMDILIntrinsicInfo.cpp

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AMDILIntrinsicInfo.h

…

AMDILIntrinsics.td

…

AMDILISelDAGToDAG.cpp

ArrayRefize getMachineNode(). No functionality change.

2013-04-19 22:22:57 +00:00

AMDILISelLowering.cpp

R600: Swap the legality of rotl and rotr

2013-05-20 15:02:19 +00:00

AMDILNIDevice.cpp

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AMDILNIDevice.h

…

AMDILRegisterInfo.td

…

AMDILSIDevice.cpp

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AMDILSIDevice.h

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CMakeLists.txt

R600: Improve texture handling

2013-05-17 16:50:20 +00:00

LLVMBuild.txt

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Makefile

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Processors.td

R600/SI: Add processor type for Hainan asic

2013-05-14 14:42:56 +00:00

R600ControlFlowFinalizer.cpp

R600: Some factorization

2013-05-17 16:50:02 +00:00

R600Defines.h

R600: Relax some vector constraints on Dot4.

2013-05-17 16:50:32 +00:00

R600EmitClauseMarkers.cpp

R600: Relax some vector constraints on Dot4.

2013-05-17 16:50:32 +00:00

R600ExpandSpecialInstrs.cpp

R600: Relax some vector constraints on Dot4.

2013-05-17 16:50:32 +00:00

R600InstrInfo.cpp

R600: Relax some vector constraints on Dot4.

2013-05-17 16:50:32 +00:00

R600InstrInfo.h

R600: Relax some vector constraints on Dot4.

2013-05-17 16:50:32 +00:00

R600Instructions.td

R600: Swap the legality of rotl and rotr

2013-05-20 15:02:19 +00:00

R600Intrinsics.td

R600: Improve texture handling

2013-05-17 16:50:20 +00:00

R600ISelLowering.cpp

R600: Swap the legality of rotl and rotr

2013-05-20 15:02:19 +00:00

R600ISelLowering.h

Add LLVMContext argument to getSetCCResultType

2013-05-18 00:21:46 +00:00

R600MachineFunctionInfo.cpp

…

R600MachineFunctionInfo.h

R600: Use .AMDGPU.config section to emit stacksize

2013-04-23 17:34:12 +00:00

R600MachineScheduler.cpp

R600: Use bottom up scheduling algorithm

2013-05-17 16:50:56 +00:00

R600MachineScheduler.h

R600: Use bottom up scheduling algorithm

2013-05-17 16:50:56 +00:00

R600Packetizer.cpp

R600: Relax some vector constraints on Dot4.

2013-05-17 16:50:32 +00:00

R600RegisterInfo.cpp

R600: Use bottom up scheduling algorithm

2013-05-17 16:50:56 +00:00

R600RegisterInfo.h

R600: Use bottom up scheduling algorithm

2013-05-17 16:50:56 +00:00

R600RegisterInfo.td

R600: Rename 128 bit registers.

2013-05-17 16:50:09 +00:00

R600Schedule.td

R600: Rework Scheduling to handle difference between VLIW4 and VLIW5 chips

2013-04-30 00:14:17 +00:00

R600TextureIntrinsicsReplacer.cpp

R600: Fix bug detected by GCC warning.

2013-05-20 15:58:43 +00:00

SIAnnotateControlFlow.cpp

…

SIDefines.h

R600/SI: Emit config values in register value pairs.

2013-04-15 17:51:35 +00:00

SIInsertWaits.cpp

…

SIInstrFormats.td

R600/SI: Use the same names for VOP3 operands and encoding fields

2013-05-20 15:02:08 +00:00

SIInstrInfo.cpp

R600/SI: dynamical figure out the reg class of MIMG

2013-04-10 08:39:16 +00:00

SIInstrInfo.h

R600/SI: adjust writemask to only the used components

2013-04-10 08:39:08 +00:00

SIInstrInfo.td

R600/SI: Use a multiclass for MUBUF_Load_Helper

2013-05-20 15:02:31 +00:00

SIInstructions.td

R600/SI: Use a multiclass for MUBUF_Load_Helper

2013-05-20 15:02:31 +00:00

SIIntrinsics.td

R600/SI: Add intrinsic for MIMG IMAGE_GET_RESINFO opcode

2013-05-06 23:02:19 +00:00

SIISelLowering.cpp

R600/SI: Make fitsRegClass() operands const

2013-05-20 15:02:01 +00:00

SIISelLowering.h

R600/SI: Make fitsRegClass() operands const

2013-05-20 15:02:01 +00:00

SILowerControlFlow.cpp

…

SIMachineFunctionInfo.cpp

…

SIMachineFunctionInfo.h

…

SIRegisterInfo.cpp

…

SIRegisterInfo.h

…

SIRegisterInfo.td

R600/SI: dynamical figure out the reg class of MIMG

2013-04-10 08:39:16 +00:00

SISchedule.td

…