llvm/test/MC/Disassembler
2013-11-13 13:15:03 +00:00
..
AArch64 [AArch64] Implemented AdvSIMD scalar x indexed element format and AdvSIMD scalar 2013-11-12 19:13:08 +00:00
ARM [ARM] Add support for MVFR2 which is new in ARMv8 2013-11-11 19:56:13 +00:00
Mips Support for microMIPS trap instruction with immediate operands. 2013-11-13 13:15:03 +00:00
SystemZ [SystemZ] Add comparisons of high words and memory 2013-10-01 15:00:44 +00:00
X86 Add disassembler support for SSE4.1 register/register form of PEXTRW. There is a shorter encoding that was part of SSE2, but a memory form was added in SSE4.1. This is the register form of that encoding. 2013-10-14 01:42:32 +00:00
XCore [tests] Cleanup initialization of test suffixes. 2013-08-16 00:37:11 +00:00