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llvm/lib/Target/R600
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Michael Gottesman c15c64fbeb Add llvm namespace to llvm::next. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189912 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-04 04:26:09 +00:00
..
InstPrinter
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MCTargetDesc
Remove unused stdio.h includes
2013-08-18 08:29:51 +00:00
TargetInfo
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AMDGPU.h
R600/SI: Convert v16i8 resource descriptors to i128
2013-08-14 23:24:45 +00:00
AMDGPU.td
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AMDGPUAsmPrinter.cpp
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AMDGPUAsmPrinter.h
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AMDGPUCallingConv.td
R600/SI: Fix an obvious typo
2013-08-14 22:22:03 +00:00
AMDGPUConvertToISA.cpp
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AMDGPUFrameLowering.cpp
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AMDGPUFrameLowering.h
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AMDGPUIndirectAddressing.cpp
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AMDGPUInstrInfo.cpp
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AMDGPUInstrInfo.h
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AMDGPUInstrInfo.td
R600: Add support for i8 and i16 local memory stores
2013-08-26 15:05:49 +00:00
AMDGPUInstructions.td
R600: Add support for i8 and i16 local memory loads
2013-08-26 15:05:59 +00:00
AMDGPUIntrinsics.td
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AMDGPUISelDAGToDAG.cpp
Mark an unreachable code path with llvm_unreachable. Pacifies GCC.
2013-08-31 21:20:04 +00:00
AMDGPUISelLowering.cpp
R600: Add support for vector local memory loads
2013-08-26 15:06:04 +00:00
AMDGPUISelLowering.h
R600: Add support for vector local memory loads
2013-08-26 15:06:04 +00:00
AMDGPUMachineFunction.cpp
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AMDGPUMachineFunction.h
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AMDGPUMCInstLower.cpp
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AMDGPUMCInstLower.h
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AMDGPURegisterInfo.cpp
R600/SI: Lower BUILD_VECTOR to REG_SEQUENCE v2
2013-08-14 23:24:32 +00:00
AMDGPURegisterInfo.h
R600/SI: Lower BUILD_VECTOR to REG_SEQUENCE v2
2013-08-14 23:24:32 +00:00
AMDGPURegisterInfo.td
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AMDGPUSubtarget.cpp
SelectionDAG: Use correct pointer size when lowering function arguments v2
2013-08-26 15:05:36 +00:00
AMDGPUSubtarget.h
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AMDGPUTargetMachine.cpp
R600/SI: Convert v16i8 resource descriptors to i128
2013-08-14 23:24:45 +00:00
AMDGPUTargetMachine.h
SimplifyCFG: Use parallel-and and parallel-or mode to consolidate branch conditions
2013-07-27 00:01:07 +00:00
AMDGPUTargetTransformInfo.cpp
SimplifyCFG: Use parallel-and and parallel-or mode to consolidate branch conditions
2013-07-27 00:01:07 +00:00
AMDILBase.td
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AMDILCFGStructurizer.cpp
Add llvm namespace to llvm::next.
2013-09-04 04:26:09 +00:00
AMDILInstrInfo.td
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AMDILIntrinsicInfo.cpp
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AMDILIntrinsicInfo.h
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AMDILIntrinsics.td
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AMDILISelLowering.cpp
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AMDILRegisterInfo.td
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CMakeLists.txt
R600/SI: Convert v16i8 resource descriptors to i128
2013-08-14 23:24:45 +00:00
LLVMBuild.txt
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Makefile
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Processors.td
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R600ControlFlowFinalizer.cpp
R600: Add IsExport bit to TableGen instruction definitions
2013-08-16 01:11:51 +00:00
R600Defines.h
R600: Add support for i8 and i16 local memory stores
2013-08-26 15:05:49 +00:00
R600EmitClauseMarkers.cpp
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R600ExpandSpecialInstrs.cpp
R600: Remove predicated_break inst
2013-07-31 19:31:14 +00:00
R600InstrFormats.td
R600: Add support for i8 and i16 local memory stores
2013-08-26 15:05:49 +00:00
R600InstrInfo.cpp
R600: Add support for i8 and i16 local memory stores
2013-08-26 15:05:49 +00:00
R600InstrInfo.h
R600: Add IsExport bit to TableGen instruction definitions
2013-08-16 01:11:51 +00:00
R600Instructions.td
R600: Add support for i8 and i16 local memory loads
2013-08-26 15:05:59 +00:00
R600Intrinsics.td
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R600ISelLowering.cpp
R600: Add support for vector local memory loads
2013-08-26 15:06:04 +00:00
R600ISelLowering.h
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R600MachineFunctionInfo.cpp
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R600MachineFunctionInfo.h
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R600MachineScheduler.cpp
Revert "R600: Non vector only instruction can be scheduled on trans unit"
2013-07-31 20:43:27 +00:00
R600MachineScheduler.h
Revert "R600: Non vector only instruction can be scheduled on trans unit"
2013-07-31 20:43:27 +00:00
R600OptimizeVectorRegisters.cpp
R600: Enable folding of inline literals into REQ_SEQUENCE instructions
2013-08-16 01:11:55 +00:00
R600Packetizer.cpp
Revert "R600: Non vector only instruction can be scheduled on trans unit"
2013-07-31 20:43:27 +00:00
R600RegisterInfo.cpp
R600/SI: Lower BUILD_VECTOR to REG_SEQUENCE v2
2013-08-14 23:24:32 +00:00
R600RegisterInfo.h
R600/SI: Lower BUILD_VECTOR to REG_SEQUENCE v2
2013-08-14 23:24:32 +00:00
R600RegisterInfo.td
R600: Add 64-bit float load/store support
2013-08-01 15:23:42 +00:00
R600Schedule.td
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R600TextureIntrinsicsReplacer.cpp
R600: Fix possible use of an uninitialized variable
2013-08-17 00:06:51 +00:00
SIAnnotateControlFlow.cpp
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SIDefines.h
R600/SI: Fix broken encoding of DS_WRITE_B32
2013-08-16 16:19:24 +00:00
SIFixSGPRCopies.cpp
R600/SI: Fix another case of illegal VGPR to SGPR copy
2013-08-22 20:21:02 +00:00
SIInsertWaits.cpp
R600/SI: Fix broken encoding of DS_WRITE_B32
2013-08-16 16:19:24 +00:00
SIInstrFormats.td
R600/SI: Fix broken encoding of DS_WRITE_B32
2013-08-16 16:19:24 +00:00
SIInstrInfo.cpp
Remove unused stdio.h includes
2013-08-18 08:29:51 +00:00
SIInstrInfo.h
R600/SI: Fix broken encoding of DS_WRITE_B32
2013-08-16 16:19:24 +00:00
SIInstrInfo.td
Revert "R600/SI: Fix incorrect encoding of DS_WRITE_B32 instructions"
2013-08-16 01:18:43 +00:00
SIInstructions.td
R600: Add support for i8 and i16 local memory loads
2013-08-26 15:05:59 +00:00
SIIntrinsics.td
R600/SI: Convert v16i8 resource descriptors to i128
2013-08-14 23:24:45 +00:00
SIISelLowering.cpp
R600: Add support for vector local memory loads
2013-08-26 15:06:04 +00:00
SIISelLowering.h
R600/SI: Improve legalization of vector operations
2013-08-14 23:25:00 +00:00
SILowerControlFlow.cpp
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SIMachineFunctionInfo.cpp
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SIMachineFunctionInfo.h
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SIRegisterInfo.cpp
R600/SI: Choose the correct MOV instruction for copying immediates
2013-08-14 23:24:24 +00:00
SIRegisterInfo.h
R600/SI: Choose the correct MOV instruction for copying immediates
2013-08-14 23:24:24 +00:00
SIRegisterInfo.td
R600/SI: Convert v16i8 resource descriptors to i128
2013-08-14 23:24:45 +00:00
SISchedule.td
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SITypeRewriter.cpp
R600/SI: Replace v1i32 type with i32 in imageload and sample intrinsics
2013-08-14 23:24:53 +00:00