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922d314e8f
Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT. Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches. Adds a test to verify that the scheduler is working. Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP. Patch by Preston Gurd! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149558 91177308-0d34-0410-b5e6-96231b3b80d8
48 lines
1.2 KiB
LLVM
48 lines
1.2 KiB
LLVM
;; X's live range extends beyond the shift, so the register allocator
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;; cannot coalesce it with Y. Because of this, a copy needs to be
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;; emitted before the shift to save the register value before it is
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;; clobbered. However, this copy is not needed if the register
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;; allocator turns the shift into an LEA. This also occurs for ADD.
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; Check that the shift gets turned into an LEA.
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; RUN: llc < %s -mcpu=generic -mtriple=x86_64-apple-darwin | FileCheck %s
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@G = external global i32
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define i32 @test1(i32 %X) nounwind {
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; CHECK: test1:
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; CHECK-NOT: mov
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; CHECK: leal 1(%rdi)
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%Z = add i32 %X, 1
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store volatile i32 %Z, i32* @G
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ret i32 %X
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}
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; rdar://8977508
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; The second add should not be transformed to leal nor should it be
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; commutted (which would require inserting a copy).
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define i32 @test2(i32 inreg %a, i32 inreg %b, i32 %c, i32 %d) nounwind {
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entry:
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; CHECK: test2:
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; CHECK: leal
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; CHECK-NOT: leal
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; CHECK-NOT: mov
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; CHECK-NEXT: addl
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; CHECK-NEXT: ret
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%add = add i32 %b, %a
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%add3 = add i32 %add, %c
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%add5 = add i32 %add3, %d
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ret i32 %add5
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}
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; rdar://9002648
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define i64 @test3(i64 %x) nounwind readnone ssp {
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entry:
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; CHECK: test3:
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; CHECK: leaq (%rdi,%rdi), %rax
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; CHECK-NOT: addq
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; CHECK-NEXT: ret
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%0 = shl i64 %x, 1
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ret i64 %0
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}
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