Craig Topper c1b9fa26d9 [X86] Post process the DAG after isel to remove vector moves that were added to zero upper bits. ...

We previously avoided inserting these moves during isel in a few cases which is implemented using a whitelist of opcodes. But it's too difficult to generate a perfect list of opcodes to whitelist. Especially with AVX512F without AVX512VL using 512 bit vectors to implement some 128/256 bit operations. Since isel is done bottoms up, we'd have to check the VT and opcode and subtarget in order to determine whether an EXTRACT_SUBREG would be generated for some operations.

So instead of doing that, this patch adds a post processing step that detects when the moves are unnecesssary after isel. At that point any EXTRACT_SUBREGs would have already been created and appear in the DAG. So then we just need to ensure the input to the move isn't one.

Differential Revision: https://reviews.llvm.org/D44289

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327724 91177308-0d34-0410-b5e6-96231b3b80d8

2018-03-16 17:13:42 +00:00

..

AArch64

[AArch64] Codegen tests for the Armv8.2-A FP16 intrinsics

2018-03-15 13:42:28 +00:00

AMDGPU

[AMDGPU][MC][GFX8][GFX9][DISASSEMBLER] Added "_e32" suffix to 32-bit VINTRP opcodes

2018-03-16 16:38:04 +00:00

ARC

[ARC] Add ARC backend.

2017-08-24 15:40:33 +00:00

ARM

[ARM] FP16 codegen support for VSEL

2018-03-16 08:06:25 +00:00

AVR

[AVR] Remove the earlyclobber flag from LDDWRdYQ

2018-03-06 11:20:25 +00:00

BPF

bpf: Extends zero extension elimination beyond comparison instructions

2018-03-13 06:47:03 +00:00

Generic

Revert "Reapply "[DWARFv5] Emit file 0 to the line table.""

2018-03-07 16:27:44 +00:00

Hexagon

[Hexagon] Fix zero-extending non-HVX bool vectors

2018-03-16 15:03:37 +00:00

Inputs

…

Lanai

Followup on Proposal to move MIR physical register namespace to '$' sigil.

2018-01-31 22:04:26 +00:00

Mips

[FastISel] Sink local value materializations to first use

2018-03-14 21:54:21 +00:00

MIR

[MIR] Allow frame-setup and frame-destroy on the same instruction

2018-03-13 19:53:16 +00:00

MSP430

Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)

2018-01-19 17:13:12 +00:00

Nios2

[Nios2] Arithmetic instructions for R1 and R2 ISA.

2018-01-09 11:15:08 +00:00

NVPTX

[DAGCombiner] When combining zero_extend of a truncate, only mask before extending for vectors.

2018-03-01 22:32:25 +00:00

PowerPC

[PPC] Avoid non-simple MVT in STBRX optimization

2018-03-15 17:49:12 +00:00

RISCV

[RISCV] Update two tests after r326208

2018-02-28 08:20:47 +00:00

SPARC

Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"

2018-02-27 16:59:10 +00:00

SystemZ

[CodeGenPrepare] Respect endianness in splitMergedValStore.

2018-03-13 08:36:20 +00:00

Thumb

[ARM] Fix access to stack arguments when re-aligning SP in Armv6m

2018-03-02 15:47:14 +00:00

Thumb2

ARM: Don't rewrite add reg, $sp, 0 -> mov reg, $sp if the add defines CPSR.

2018-02-27 19:00:59 +00:00

WebAssembly

[WebAssembly] Add mechanisms for specifying an explicit import module name.

2018-02-09 23:13:22 +00:00

WinCFGuard

Reland "Emit Function IDs table for Control Flow Guard"

2018-01-09 23:49:30 +00:00

WinEH

Make x86 __ehhandler comdat if parent function is

2017-10-20 17:04:43 +00:00

X86

[X86] Post process the DAG after isel to remove vector moves that were added to zero upper bits.

2018-03-16 17:13:42 +00:00

XCore

[XCore] Return true in enableMultipleCopyHints().

2018-02-26 08:03:32 +00:00