Matt Arsenault c205b62417 Move AArch64BranchRelaxation to generic code ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283459 91177308-0d34-0410-b5e6-96231b3b80d8

2016-10-06 15:38:53 +00:00

..

cfi-def-cfa.mir

MIRParser: Use shorter cfi identifiers

2016-07-26 18:20:00 +00:00

expected-target-flag-name.mir

llc: Add support for -run-pass none

2016-07-16 02:24:59 +00:00

generic-virtual-registers-error.mir

MIRParser/MIRPrinter: Compute isSSA instead of printing/parsing it.

2016-08-24 01:32:41 +00:00

generic-virtual-registers-with-regbank-error.mir

MIRParser/MIRPrinter: Compute isSSA instead of printing/parsing it.

2016-08-24 01:32:41 +00:00

inst-size-patchpoint.mir

Move AArch64BranchRelaxation to generic code

2016-10-06 15:38:53 +00:00

inst-size-stackmap.mir

Move AArch64BranchRelaxation to generic code

2016-10-06 15:38:53 +00:00

inst-size-tlsdesc-callseq.mir

Move AArch64BranchRelaxation to generic code

2016-10-06 15:38:53 +00:00

intrinsics.mir

CodeGen: add new "intrinsic" MachineOperand kind.

2016-07-29 20:32:59 +00:00

invalid-target-flag-name.mir

llc: Add support for -run-pass none

2016-07-16 02:24:59 +00:00

lit.local.cfg

…

machine-dead-copy.mir

MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, compute it

2016-08-25 01:27:13 +00:00

machine-scheduler.mir

MIRParser/MIRPrinter: Compute isSSA instead of printing/parsing it.

2016-08-24 01:32:41 +00:00

machine-sink-zr.mir

[TargetRegisterInfo, AArch64] Add target hook for isConstantPhysReg().

2016-09-27 22:17:27 +00:00

multiple-lhs-operands.mir

llc: Add support for -run-pass none

2016-07-16 02:24:59 +00:00

stack-object-local-offset.mir

MIRParser/MIRPrinter: Compute isSSA instead of printing/parsing it.

2016-08-24 01:32:41 +00:00

target-flags.mir

llc: Add support for -run-pass none

2016-07-16 02:24:59 +00:00