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to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351636 91177308-0d34-0410-b5e6-96231b3b80d8
36 lines
1.2 KiB
C++
36 lines
1.2 KiB
C++
//===- RISCVMatInt.h - Immediate materialisation ---------------*- C++ -*--===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_RISCV_MATINT_H
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#define LLVM_LIB_TARGET_RISCV_MATINT_H
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/Support/MachineValueType.h"
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#include <cstdint>
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namespace llvm {
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namespace RISCVMatInt {
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struct Inst {
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unsigned Opc;
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int64_t Imm;
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Inst(unsigned Opc, int64_t Imm) : Opc(Opc), Imm(Imm) {}
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};
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using InstSeq = SmallVector<Inst, 8>;
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// Helper to generate an instruction sequence that will materialise the given
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// immediate value into a register. A sequence of instructions represented by
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// a simple struct produced rather than directly emitting the instructions in
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// order to allow this helper to be used from both the MC layer and during
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// instruction selection.
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void generateInstSeq(int64_t Val, bool IsRV64, InstSeq &Res);
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} // namespace RISCVMatInt
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} // namespace llvm
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#endif
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