mirror of
https://github.com/RPCS3/llvm.git
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776a459079
Summary: Instead of writing boolean values temporarily into 32-bit VGPRs if they are involved in PHIs or are observed from outside a loop, we use bitwise masking operations to combine lane masks in a way that is consistent with wave control flow. Move SIFixSGPRCopies to before this pass, since that pass incorrectly attempts to move SGPR phis to VGPRs. This should recover most of the code quality that was lost with the bug fix in "AMDGPU: Remove PHI loop condition optimization". There are still some relevant cases where code quality could be improved, in particular: - We often introduce redundant masks with EXEC. Ideally, we'd have a generic computeKnownBits-like analysis to determine whether masks are already masked by EXEC, so we can avoid this masking both here and when lowering uniform control flow. - The criterion we use to determine whether a def is observed from outside a loop is conservative: it doesn't check whether (loop) branch conditions are uniform. Change-Id: Ibabdb373a7510e426b90deef00f5e16c5d56e64b Reviewers: arsenm, rampitec, tpr Subscribers: kzhuravl, jvesely, wdng, mgorny, yaxunl, dstuttard, t-tye, eraman, llvm-commits Differential Revision: https://reviews.llvm.org/D53496 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345719 91177308-0d34-0410-b5e6-96231b3b80d8
336 lines
12 KiB
LLVM
336 lines
12 KiB
LLVM
; RUN: opt -mtriple=amdgcn-- -S -structurizecfg -si-annotate-control-flow %s | FileCheck -check-prefix=OPT %s
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; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; Uses llvm.amdgcn.break
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; OPT-LABEL: @break_loop(
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; OPT: bb1:
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; OPT: icmp slt i32
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; OPT-NEXT: br i1 %cmp0, label %bb4, label %Flow
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; OPT: bb4:
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; OPT: load volatile
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; OPT: icmp slt i32
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; OPT: xor i1 %cmp1
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; OPT: br label %Flow
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; OPT: Flow:
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; OPT: call i64 @llvm.amdgcn.if.break(
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; OPT: call i1 @llvm.amdgcn.loop(i64
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; OPT: br i1 %{{[0-9]+}}, label %bb9, label %bb1
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; OPT: bb9:
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; OPT: call void @llvm.amdgcn.end.cf(i64
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; GCN-LABEL: {{^}}break_loop:
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; GCN: s_mov_b64 [[OUTER_MASK:s\[[0-9]+:[0-9]+\]]], 0{{$}}
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; GCN: [[LOOP_ENTRY:BB[0-9]+_[0-9]+]]: ; %bb1
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; GCN: v_cmp_lt_i32_e32 vcc, -1
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; GCN: s_and_b64 vcc, exec, vcc
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; GCN: s_or_b64 [[INNER_MASK:s\[[0-9]+:[0-9]+\]]], [[INNER_MASK]], exec
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; GCN: s_cbranch_vccnz [[FLOW:BB[0-9]+_[0-9]+]]
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; GCN: ; %bb4
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; GCN: buffer_load_dword
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; GCN: v_cmp_ge_i32_e32 vcc,
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; GCN: s_andn2_b64 [[INNER_MASK]], [[INNER_MASK]], exec
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; GCN: s_and_b64 [[TMP0:s\[[0-9]+:[0-9]+\]]], vcc, exec
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; GCN: s_or_b64 [[INNER_MASK]], [[INNER_MASK]], [[TMP0]]
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; GCN: [[FLOW]]: ; %Flow
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; GCN: s_and_b64 [[TMP1:s\[[0-9]+:[0-9]+\]]], exec, [[INNER_MASK]]
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; GCN: s_or_b64 [[TMP1]], [[TMP1]], [[OUTER_MASK]]
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; GCN: s_mov_b64 [[OUTER_MASK]], [[TMP1]]
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; GCN: s_andn2_b64 exec, exec, [[TMP1]]
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; GCN-NEXT: s_cbranch_execnz [[LOOP_ENTRY]]
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; GCN: ; %bb.4: ; %bb9
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; GCN-NEXT: s_endpgm
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define amdgpu_kernel void @break_loop(i32 %arg) #0 {
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bb:
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%id = call i32 @llvm.amdgcn.workitem.id.x()
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%tmp = sub i32 %id, %arg
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br label %bb1
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bb1:
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%lsr.iv = phi i32 [ undef, %bb ], [ %lsr.iv.next, %bb4 ]
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%lsr.iv.next = add i32 %lsr.iv, 1
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%cmp0 = icmp slt i32 %lsr.iv.next, 0
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br i1 %cmp0, label %bb4, label %bb9
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bb4:
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%load = load volatile i32, i32 addrspace(1)* undef, align 4
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%cmp1 = icmp slt i32 %tmp, %load
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br i1 %cmp1, label %bb1, label %bb9
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bb9:
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ret void
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}
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; OPT-LABEL: @undef_phi_cond_break_loop(
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; OPT: bb1:
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; OPT-NEXT: %phi.broken = phi i64 [ %0, %Flow ], [ 0, %bb ]
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; OPT-NEXT: %lsr.iv = phi i32 [ undef, %bb ], [ %tmp2, %Flow ]
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; OPT-NEXT: %lsr.iv.next = add i32 %lsr.iv, 1
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; OPT-NEXT: %cmp0 = icmp slt i32 %lsr.iv.next, 0
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; OPT-NEXT: br i1 %cmp0, label %bb4, label %Flow
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; OPT: bb4:
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; OPT-NEXT: %load = load volatile i32, i32 addrspace(1)* undef, align 4
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; OPT-NEXT: %cmp1 = icmp sge i32 %tmp, %load
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; OPT-NEXT: br label %Flow
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; OPT: Flow:
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; OPT-NEXT: %tmp2 = phi i32 [ %lsr.iv.next, %bb4 ], [ undef, %bb1 ]
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; OPT-NEXT: %tmp3 = phi i1 [ %cmp1, %bb4 ], [ undef, %bb1 ]
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; OPT-NEXT: %0 = call i64 @llvm.amdgcn.if.break(i1 %tmp3, i64 %phi.broken)
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; OPT-NEXT: %1 = call i1 @llvm.amdgcn.loop(i64 %0)
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; OPT-NEXT: br i1 %1, label %bb9, label %bb1
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; OPT: bb9: ; preds = %Flow
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; OPT-NEXT: call void @llvm.amdgcn.end.cf(i64 %0)
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; OPT-NEXT: store volatile i32 7
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; OPT-NEXT: ret void
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define amdgpu_kernel void @undef_phi_cond_break_loop(i32 %arg) #0 {
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bb:
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%id = call i32 @llvm.amdgcn.workitem.id.x()
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%tmp = sub i32 %id, %arg
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br label %bb1
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bb1: ; preds = %Flow, %bb
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%lsr.iv = phi i32 [ undef, %bb ], [ %tmp2, %Flow ]
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%lsr.iv.next = add i32 %lsr.iv, 1
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%cmp0 = icmp slt i32 %lsr.iv.next, 0
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br i1 %cmp0, label %bb4, label %Flow
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bb4: ; preds = %bb1
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%load = load volatile i32, i32 addrspace(1)* undef, align 4
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%cmp1 = icmp sge i32 %tmp, %load
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br label %Flow
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Flow: ; preds = %bb4, %bb1
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%tmp2 = phi i32 [ %lsr.iv.next, %bb4 ], [ undef, %bb1 ]
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%tmp3 = phi i1 [ %cmp1, %bb4 ], [ undef, %bb1 ]
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br i1 %tmp3, label %bb9, label %bb1
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bb9: ; preds = %Flow
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store volatile i32 7, i32 addrspace(3)* undef
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ret void
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}
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; FIXME: ConstantExpr compare of address to null folds away
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@lds = addrspace(3) global i32 undef
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; OPT-LABEL: @constexpr_phi_cond_break_loop(
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; OPT: bb1:
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; OPT-NEXT: %phi.broken = phi i64 [ %0, %Flow ], [ 0, %bb ]
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; OPT-NEXT: %lsr.iv = phi i32 [ undef, %bb ], [ %tmp2, %Flow ]
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; OPT-NEXT: %lsr.iv.next = add i32 %lsr.iv, 1
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; OPT-NEXT: %cmp0 = icmp slt i32 %lsr.iv.next, 0
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; OPT-NEXT: br i1 %cmp0, label %bb4, label %Flow
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; OPT: bb4:
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; OPT-NEXT: %load = load volatile i32, i32 addrspace(1)* undef, align 4
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; OPT-NEXT: %cmp1 = icmp sge i32 %tmp, %load
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; OPT-NEXT: br label %Flow
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; OPT: Flow:
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; OPT-NEXT: %tmp2 = phi i32 [ %lsr.iv.next, %bb4 ], [ undef, %bb1 ]
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; OPT-NEXT: %tmp3 = phi i1 [ %cmp1, %bb4 ], [ icmp ne (i32 addrspace(3)* inttoptr (i32 4 to i32 addrspace(3)*), i32 addrspace(3)* @lds), %bb1 ]
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; OPT-NEXT: %0 = call i64 @llvm.amdgcn.if.break(i1 %tmp3, i64 %phi.broken)
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; OPT-NEXT: %1 = call i1 @llvm.amdgcn.loop(i64 %0)
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; OPT-NEXT: br i1 %1, label %bb9, label %bb1
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; OPT: bb9: ; preds = %Flow
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; OPT-NEXT: call void @llvm.amdgcn.end.cf(i64 %0)
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; OPT-NEXT: store volatile i32 7
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; OPT-NEXT: ret void
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define amdgpu_kernel void @constexpr_phi_cond_break_loop(i32 %arg) #0 {
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bb:
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%id = call i32 @llvm.amdgcn.workitem.id.x()
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%tmp = sub i32 %id, %arg
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br label %bb1
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bb1: ; preds = %Flow, %bb
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%lsr.iv = phi i32 [ undef, %bb ], [ %tmp2, %Flow ]
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%lsr.iv.next = add i32 %lsr.iv, 1
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%cmp0 = icmp slt i32 %lsr.iv.next, 0
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br i1 %cmp0, label %bb4, label %Flow
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bb4: ; preds = %bb1
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%load = load volatile i32, i32 addrspace(1)* undef, align 4
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%cmp1 = icmp sge i32 %tmp, %load
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br label %Flow
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Flow: ; preds = %bb4, %bb1
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%tmp2 = phi i32 [ %lsr.iv.next, %bb4 ], [ undef, %bb1 ]
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%tmp3 = phi i1 [ %cmp1, %bb4 ], [ icmp ne (i32 addrspace(3)* inttoptr (i32 4 to i32 addrspace(3)*), i32 addrspace(3)* @lds), %bb1 ]
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br i1 %tmp3, label %bb9, label %bb1
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bb9: ; preds = %Flow
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store volatile i32 7, i32 addrspace(3)* undef
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ret void
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}
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; OPT-LABEL: @true_phi_cond_break_loop(
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; OPT: bb1:
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; OPT-NEXT: %phi.broken = phi i64 [ %0, %Flow ], [ 0, %bb ]
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; OPT-NEXT: %lsr.iv = phi i32 [ undef, %bb ], [ %tmp2, %Flow ]
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; OPT-NEXT: %lsr.iv.next = add i32 %lsr.iv, 1
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; OPT-NEXT: %cmp0 = icmp slt i32 %lsr.iv.next, 0
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; OPT-NEXT: br i1 %cmp0, label %bb4, label %Flow
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; OPT: bb4:
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; OPT-NEXT: %load = load volatile i32, i32 addrspace(1)* undef, align 4
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; OPT-NEXT: %cmp1 = icmp sge i32 %tmp, %load
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; OPT-NEXT: br label %Flow
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; OPT: Flow:
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; OPT-NEXT: %tmp2 = phi i32 [ %lsr.iv.next, %bb4 ], [ undef, %bb1 ]
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; OPT-NEXT: %tmp3 = phi i1 [ %cmp1, %bb4 ], [ true, %bb1 ]
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; OPT-NEXT: %0 = call i64 @llvm.amdgcn.if.break(i1 %tmp3, i64 %phi.broken)
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; OPT-NEXT: %1 = call i1 @llvm.amdgcn.loop(i64 %0)
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; OPT-NEXT: br i1 %1, label %bb9, label %bb1
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; OPT: bb9: ; preds = %Flow
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; OPT-NEXT: call void @llvm.amdgcn.end.cf(i64 %0)
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; OPT-NEXT: store volatile i32 7
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; OPT-NEXT: ret void
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define amdgpu_kernel void @true_phi_cond_break_loop(i32 %arg) #0 {
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bb:
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%id = call i32 @llvm.amdgcn.workitem.id.x()
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%tmp = sub i32 %id, %arg
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br label %bb1
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bb1: ; preds = %Flow, %bb
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%lsr.iv = phi i32 [ undef, %bb ], [ %tmp2, %Flow ]
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%lsr.iv.next = add i32 %lsr.iv, 1
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%cmp0 = icmp slt i32 %lsr.iv.next, 0
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br i1 %cmp0, label %bb4, label %Flow
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bb4: ; preds = %bb1
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%load = load volatile i32, i32 addrspace(1)* undef, align 4
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%cmp1 = icmp sge i32 %tmp, %load
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br label %Flow
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Flow: ; preds = %bb4, %bb1
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%tmp2 = phi i32 [ %lsr.iv.next, %bb4 ], [ undef, %bb1 ]
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%tmp3 = phi i1 [ %cmp1, %bb4 ], [ true, %bb1 ]
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br i1 %tmp3, label %bb9, label %bb1
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bb9: ; preds = %Flow
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store volatile i32 7, i32 addrspace(3)* undef
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ret void
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}
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; OPT-LABEL: @false_phi_cond_break_loop(
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; OPT: bb1:
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; OPT-NEXT: %phi.broken = phi i64 [ %0, %Flow ], [ 0, %bb ]
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; OPT-NEXT: %lsr.iv = phi i32 [ undef, %bb ], [ %tmp2, %Flow ]
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; OPT-NOT: call
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; OPT: br i1 %cmp0, label %bb4, label %Flow
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; OPT: bb4:
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; OPT-NEXT: %load = load volatile i32, i32 addrspace(1)* undef, align 4
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; OPT-NEXT: %cmp1 = icmp sge i32 %tmp, %load
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; OPT-NEXT: br label %Flow
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; OPT: Flow:
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; OPT-NEXT: %tmp2 = phi i32 [ %lsr.iv.next, %bb4 ], [ undef, %bb1 ]
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; OPT-NEXT: %tmp3 = phi i1 [ %cmp1, %bb4 ], [ false, %bb1 ]
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; OPT-NEXT: %0 = call i64 @llvm.amdgcn.if.break(i1 %tmp3, i64 %phi.broken)
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; OPT-NEXT: %1 = call i1 @llvm.amdgcn.loop(i64 %0)
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; OPT-NEXT: br i1 %1, label %bb9, label %bb1
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; OPT: bb9: ; preds = %Flow
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; OPT-NEXT: call void @llvm.amdgcn.end.cf(i64 %0)
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; OPT-NEXT: store volatile i32 7
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; OPT-NEXT: ret void
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define amdgpu_kernel void @false_phi_cond_break_loop(i32 %arg) #0 {
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bb:
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%id = call i32 @llvm.amdgcn.workitem.id.x()
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%tmp = sub i32 %id, %arg
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br label %bb1
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bb1: ; preds = %Flow, %bb
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%lsr.iv = phi i32 [ undef, %bb ], [ %tmp2, %Flow ]
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%lsr.iv.next = add i32 %lsr.iv, 1
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%cmp0 = icmp slt i32 %lsr.iv.next, 0
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br i1 %cmp0, label %bb4, label %Flow
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bb4: ; preds = %bb1
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%load = load volatile i32, i32 addrspace(1)* undef, align 4
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%cmp1 = icmp sge i32 %tmp, %load
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br label %Flow
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Flow: ; preds = %bb4, %bb1
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%tmp2 = phi i32 [ %lsr.iv.next, %bb4 ], [ undef, %bb1 ]
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%tmp3 = phi i1 [ %cmp1, %bb4 ], [ false, %bb1 ]
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br i1 %tmp3, label %bb9, label %bb1
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bb9: ; preds = %Flow
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store volatile i32 7, i32 addrspace(3)* undef
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ret void
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}
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; Swap order of branches in flow block so that the true phi is
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; continue.
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; OPT-LABEL: @invert_true_phi_cond_break_loop(
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; OPT: bb1:
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; OPT-NEXT: %phi.broken = phi i64 [ %1, %Flow ], [ 0, %bb ]
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; OPT-NEXT: %lsr.iv = phi i32 [ undef, %bb ], [ %tmp2, %Flow ]
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; OPT-NEXT: %lsr.iv.next = add i32 %lsr.iv, 1
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; OPT-NEXT: %cmp0 = icmp slt i32 %lsr.iv.next, 0
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; OPT-NEXT: br i1 %cmp0, label %bb4, label %Flow
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; OPT: bb4:
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; OPT-NEXT: %load = load volatile i32, i32 addrspace(1)* undef, align 4
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; OPT-NEXT: %cmp1 = icmp sge i32 %tmp, %load
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; OPT-NEXT: br label %Flow
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; OPT: Flow:
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; OPT-NEXT: %tmp2 = phi i32 [ %lsr.iv.next, %bb4 ], [ undef, %bb1 ]
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; OPT-NEXT: %tmp3 = phi i1 [ %cmp1, %bb4 ], [ true, %bb1 ]
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; OPT-NEXT: %0 = xor i1 %tmp3, true
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; OPT-NEXT: %1 = call i64 @llvm.amdgcn.if.break(i1 %0, i64 %phi.broken)
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; OPT-NEXT: %2 = call i1 @llvm.amdgcn.loop(i64 %1)
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; OPT-NEXT: br i1 %2, label %bb9, label %bb1
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; OPT: bb9:
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; OPT-NEXT: call void @llvm.amdgcn.end.cf(i64 %1)
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; OPT-NEXT: store volatile i32 7, i32 addrspace(3)* undef
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; OPT-NEXT: ret void
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define amdgpu_kernel void @invert_true_phi_cond_break_loop(i32 %arg) #0 {
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bb:
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%id = call i32 @llvm.amdgcn.workitem.id.x()
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%tmp = sub i32 %id, %arg
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br label %bb1
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bb1: ; preds = %Flow, %bb
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%lsr.iv = phi i32 [ undef, %bb ], [ %tmp2, %Flow ]
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%lsr.iv.next = add i32 %lsr.iv, 1
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%cmp0 = icmp slt i32 %lsr.iv.next, 0
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br i1 %cmp0, label %bb4, label %Flow
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bb4: ; preds = %bb1
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%load = load volatile i32, i32 addrspace(1)* undef, align 4
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%cmp1 = icmp sge i32 %tmp, %load
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br label %Flow
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Flow: ; preds = %bb4, %bb1
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%tmp2 = phi i32 [ %lsr.iv.next, %bb4 ], [ undef, %bb1 ]
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%tmp3 = phi i1 [ %cmp1, %bb4 ], [ true, %bb1 ]
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br i1 %tmp3, label %bb1, label %bb9
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bb9: ; preds = %Flow
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store volatile i32 7, i32 addrspace(3)* undef
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #1
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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