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a328146a75
FastISel wasn't checking the isFPOnlySP subtarget feature before emitting double-precision operations, so it got completely invalid CodeGen for doubles on Cortex-M4F. The normal ISel testing wasn't spectacular either so I added a second RUN line to improve that while I was in the area. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296031 91177308-0d34-0410-b5e6-96231b3b80d8
63 lines
1.6 KiB
LLVM
63 lines
1.6 KiB
LLVM
; RUN: llc -mtriple=thumbv7em-apple-macho -mcpu=cortex-m4 %s -o - -O0 | FileCheck %s
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; RUN: llc -mtriple=thumbv7em-apple-macho -mcpu=cortex-m4 %s -o - | FileCheck %s
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; Note: vldr and vstr really do have 64-bit variants even with fp-only-sp
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define void @test_load_store(double* %addr) {
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; CHECK-LABEL: test_load_store:
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; CHECK: vldr [[TMP:d[0-9]+]], [r0]
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; CHECK: vstr [[TMP]], [r0]
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%val = load volatile double, double* %addr
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store volatile double %val, double* %addr
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ret void
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}
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define void @test_cmp(double %l, double %r, i1* %addr.dst) {
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; CHECK-LABEL: test_cmp:
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; CHECK: bl ___eqdf2
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%res = fcmp oeq double %l, %r
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store i1 %res, i1* %addr.dst
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ret void
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}
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define void @test_ext(float %in, double* %addr) {
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; CHECK-LABEL: test_ext:
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; CHECK: bl ___extendsfdf2
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%res = fpext float %in to double
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store double %res, double* %addr
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ret void
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}
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define void @test_trunc(double %in, float* %addr) {
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; CHECK-LABEL: test_trunc:
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; CHECK: bl ___truncdfsf2
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%res = fptrunc double %in to float
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store float %res, float* %addr
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ret void
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}
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define void @test_itofp(i32 %in, double* %addr) {
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; CHECK-LABEL: test_itofp:
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; CHECK: bl ___floatsidf
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%res = sitofp i32 %in to double
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store double %res, double* %addr
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; %res = fptoui double %tmp to i32
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ret void
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}
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define i32 @test_fptoi(double* %addr) {
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; CHECK-LABEL: test_fptoi:
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; CHECK: bl ___fixunsdfsi
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%val = load double, double* %addr
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%res = fptoui double %val to i32
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ret i32 %res
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}
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define void @test_binop(double* %addr) {
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; CHECK-LABEL: test_binop:
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; CHECK: bl ___adddf3
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%in = load double, double* %addr
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%res = fadd double %in, %in
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store double %res, double* %addr
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ret void
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}
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