llvm/test/CodeGen/PowerPC/ctrloop-large-ec.ll
Zi Xuan Wu 5f2a36709f [PowerPC] Fix assert from machine verify pass that missing undef register flag
Fix assert about using an undefined physical register in machine instruction verify pass. 
The reason is that register flag undef is missing when doing transformation from If Conversion Pass.

```
Bad machine code: Using an undefined physical register 
- function:    func_65
- basic block: %bb.0 entry (0x10024740738)
- instruction: BCLR killed $cr5lt, implicit $lr8, implicit $rm, implicit undef $x3
- operand 0:   killed $cr5lt
LLVM ERROR: Found 1 machine code errors.
```

There are also other existing testcases with same issue. So I add -verify-machineinstrs option to open verifying.

Differential Revision: https://reviews.llvm.org/D55408



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@348566 91177308-0d34-0410-b5e6-96231b3b80d8
2018-12-07 05:25:16 +00:00

24 lines
756 B
LLVM

; RUN: llc -mcpu=ppc32 -verify-machineinstrs < %s | FileCheck %s
target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32"
target triple = "powerpc-unknown-linux-gnu"
define void @fn1() {
entry:
br i1 undef, label %for.end, label %for.body
for.body: ; preds = %for.body, %entry
%inc3 = phi i64 [ %inc, %for.body ], [ undef, %entry ]
%inc = add nsw i64 %inc3, 1
%tobool = icmp eq i64 %inc, 0
br i1 %tobool, label %for.end, label %for.body
for.end: ; preds = %for.body, %entry
ret void
}
; On PPC32, CTR is also 32 bits, and so cannot hold a 64-bit count.
; CHECK: @fn1
; CHECK-NOT: mtctr
; CHECK: blr