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llvm/test/CodeGen
David Green 510ed947ff [ARM] MVE predicate register support
This adds support code for building and shuffling i1 predicate registers. It
generally uses two basic principles, either converting the predicate into an
scalar (through a PREDICATE_CAST) and doing scalar operations on it there, or
by converting the register to an full vector register and back.

Some of the code here is a not super efficient but will hopefully cover most
cases of moving i1 vectors around and can be improved in subsequent patches.

Some code by David Sherwood.

Differential Revision: https://reviews.llvm.org/D65052


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366890 91177308-0d34-0410-b5e6-96231b3b80d8
2019-07-24 11:51:36 +00:00
..
2019-07-04 06:12:47 +00:00