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c3ec7e2273
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194858 91177308-0d34-0410-b5e6-96231b3b80d8
675 lines
22 KiB
C++
675 lines
22 KiB
C++
//===-- SIInstrInfo.cpp - SI Instruction Information ---------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief SI Implementation of TargetInstrInfo.
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//
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//===----------------------------------------------------------------------===//
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#include "SIInstrInfo.h"
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#include "AMDGPUTargetMachine.h"
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#include "SIDefines.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/MC/MCInstrDesc.h"
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using namespace llvm;
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SIInstrInfo::SIInstrInfo(AMDGPUTargetMachine &tm)
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: AMDGPUInstrInfo(tm),
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RI(tm)
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{ }
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const SIRegisterInfo &SIInstrInfo::getRegisterInfo() const {
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return RI;
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}
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//===----------------------------------------------------------------------===//
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// TargetInstrInfo callbacks
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//===----------------------------------------------------------------------===//
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void
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SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const {
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// If we are trying to copy to or from SCC, there is a bug somewhere else in
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// the backend. While it may be theoretically possible to do this, it should
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// never be necessary.
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assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC);
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static const int16_t Sub0_15[] = {
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AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
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AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7,
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AMDGPU::sub8, AMDGPU::sub9, AMDGPU::sub10, AMDGPU::sub11,
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AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14, AMDGPU::sub15, 0
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};
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static const int16_t Sub0_7[] = {
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AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
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AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, 0
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};
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static const int16_t Sub0_3[] = {
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AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, 0
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};
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static const int16_t Sub0_2[] = {
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AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, 0
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};
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static const int16_t Sub0_1[] = {
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AMDGPU::sub0, AMDGPU::sub1, 0
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};
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unsigned Opcode;
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const int16_t *SubIndices;
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if (AMDGPU::M0 == DestReg) {
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// Check if M0 isn't already set to this value
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for (MachineBasicBlock::reverse_iterator E = MBB.rend(),
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I = MachineBasicBlock::reverse_iterator(MI); I != E; ++I) {
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if (!I->definesRegister(AMDGPU::M0))
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continue;
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unsigned Opc = I->getOpcode();
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if (Opc != TargetOpcode::COPY && Opc != AMDGPU::S_MOV_B32)
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break;
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if (!I->readsRegister(SrcReg))
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break;
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// The copy isn't necessary
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return;
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}
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}
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if (AMDGPU::SReg_32RegClass.contains(DestReg)) {
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assert(AMDGPU::SReg_32RegClass.contains(SrcReg));
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BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
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.addReg(SrcReg, getKillRegState(KillSrc));
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return;
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} else if (AMDGPU::SReg_64RegClass.contains(DestReg)) {
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assert(AMDGPU::SReg_64RegClass.contains(SrcReg));
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BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
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.addReg(SrcReg, getKillRegState(KillSrc));
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return;
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} else if (AMDGPU::SReg_128RegClass.contains(DestReg)) {
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assert(AMDGPU::SReg_128RegClass.contains(SrcReg));
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Opcode = AMDGPU::S_MOV_B32;
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SubIndices = Sub0_3;
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} else if (AMDGPU::SReg_256RegClass.contains(DestReg)) {
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assert(AMDGPU::SReg_256RegClass.contains(SrcReg));
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Opcode = AMDGPU::S_MOV_B32;
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SubIndices = Sub0_7;
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} else if (AMDGPU::SReg_512RegClass.contains(DestReg)) {
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assert(AMDGPU::SReg_512RegClass.contains(SrcReg));
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Opcode = AMDGPU::S_MOV_B32;
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SubIndices = Sub0_15;
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} else if (AMDGPU::VReg_32RegClass.contains(DestReg)) {
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assert(AMDGPU::VReg_32RegClass.contains(SrcReg) ||
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AMDGPU::SReg_32RegClass.contains(SrcReg));
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BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
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.addReg(SrcReg, getKillRegState(KillSrc));
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return;
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} else if (AMDGPU::VReg_64RegClass.contains(DestReg)) {
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assert(AMDGPU::VReg_64RegClass.contains(SrcReg) ||
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AMDGPU::SReg_64RegClass.contains(SrcReg));
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Opcode = AMDGPU::V_MOV_B32_e32;
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SubIndices = Sub0_1;
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} else if (AMDGPU::VReg_96RegClass.contains(DestReg)) {
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assert(AMDGPU::VReg_96RegClass.contains(SrcReg));
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Opcode = AMDGPU::V_MOV_B32_e32;
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SubIndices = Sub0_2;
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} else if (AMDGPU::VReg_128RegClass.contains(DestReg)) {
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assert(AMDGPU::VReg_128RegClass.contains(SrcReg) ||
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AMDGPU::SReg_128RegClass.contains(SrcReg));
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Opcode = AMDGPU::V_MOV_B32_e32;
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SubIndices = Sub0_3;
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} else if (AMDGPU::VReg_256RegClass.contains(DestReg)) {
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assert(AMDGPU::VReg_256RegClass.contains(SrcReg) ||
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AMDGPU::SReg_256RegClass.contains(SrcReg));
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Opcode = AMDGPU::V_MOV_B32_e32;
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SubIndices = Sub0_7;
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} else if (AMDGPU::VReg_512RegClass.contains(DestReg)) {
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assert(AMDGPU::VReg_512RegClass.contains(SrcReg) ||
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AMDGPU::SReg_512RegClass.contains(SrcReg));
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Opcode = AMDGPU::V_MOV_B32_e32;
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SubIndices = Sub0_15;
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} else {
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llvm_unreachable("Can't copy register!");
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}
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while (unsigned SubIdx = *SubIndices++) {
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MachineInstrBuilder Builder = BuildMI(MBB, MI, DL,
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get(Opcode), RI.getSubReg(DestReg, SubIdx));
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Builder.addReg(RI.getSubReg(SrcReg, SubIdx), getKillRegState(KillSrc));
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if (*SubIndices)
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Builder.addReg(DestReg, RegState::Define | RegState::Implicit);
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}
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}
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unsigned SIInstrInfo::commuteOpcode(unsigned Opcode) const {
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int NewOpc;
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// Try to map original to commuted opcode
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if ((NewOpc = AMDGPU::getCommuteRev(Opcode)) != -1)
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return NewOpc;
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// Try to map commuted to original opcode
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if ((NewOpc = AMDGPU::getCommuteOrig(Opcode)) != -1)
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return NewOpc;
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return Opcode;
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}
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MachineInstr *SIInstrInfo::commuteInstruction(MachineInstr *MI,
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bool NewMI) const {
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MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
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if (MI->getNumOperands() < 3 || !MI->getOperand(1).isReg())
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return 0;
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// Cannot commute VOP2 if src0 is SGPR.
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if (isVOP2(MI->getOpcode()) && MI->getOperand(1).isReg() &&
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RI.isSGPRClass(MRI.getRegClass(MI->getOperand(1).getReg())))
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return 0;
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if (!MI->getOperand(2).isReg()) {
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// XXX: Commute instructions with FPImm operands
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if (NewMI || MI->getOperand(2).isFPImm() ||
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(!isVOP2(MI->getOpcode()) && !isVOP3(MI->getOpcode()))) {
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return 0;
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}
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// XXX: Commute VOP3 instructions with abs and neg set.
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if (isVOP3(MI->getOpcode()) &&
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(MI->getOperand(AMDGPU::getNamedOperandIdx(MI->getOpcode(),
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AMDGPU::OpName::abs)).getImm() ||
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MI->getOperand(AMDGPU::getNamedOperandIdx(MI->getOpcode(),
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AMDGPU::OpName::neg)).getImm()))
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return 0;
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unsigned Reg = MI->getOperand(1).getReg();
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MI->getOperand(1).ChangeToImmediate(MI->getOperand(2).getImm());
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MI->getOperand(2).ChangeToRegister(Reg, false);
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} else {
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MI = TargetInstrInfo::commuteInstruction(MI, NewMI);
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}
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if (MI)
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MI->setDesc(get(commuteOpcode(MI->getOpcode())));
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return MI;
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}
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MachineInstr *SIInstrInfo::buildMovInstr(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator I,
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unsigned DstReg,
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unsigned SrcReg) const {
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return BuildMI(*MBB, I, MBB->findDebugLoc(I), get(AMDGPU::V_MOV_B32_e32),
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DstReg) .addReg(SrcReg);
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}
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bool SIInstrInfo::isMov(unsigned Opcode) const {
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switch(Opcode) {
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default: return false;
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case AMDGPU::S_MOV_B32:
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case AMDGPU::S_MOV_B64:
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case AMDGPU::V_MOV_B32_e32:
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case AMDGPU::V_MOV_B32_e64:
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return true;
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}
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}
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bool
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SIInstrInfo::isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
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return RC != &AMDGPU::EXECRegRegClass;
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}
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int SIInstrInfo::isMIMG(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::MIMG;
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}
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int SIInstrInfo::isSMRD(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::SMRD;
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}
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bool SIInstrInfo::isVOP1(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::VOP1;
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}
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bool SIInstrInfo::isVOP2(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::VOP2;
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}
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bool SIInstrInfo::isVOP3(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::VOP3;
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}
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bool SIInstrInfo::isVOPC(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::VOPC;
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}
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bool SIInstrInfo::isSALUInstr(const MachineInstr &MI) const {
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return get(MI.getOpcode()).TSFlags & SIInstrFlags::SALU;
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}
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bool SIInstrInfo::isInlineConstant(const MachineOperand &MO) const {
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if(MO.isImm()) {
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return MO.getImm() >= -16 && MO.getImm() <= 64;
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}
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if (MO.isFPImm()) {
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return MO.getFPImm()->isExactlyValue(0.0) ||
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MO.getFPImm()->isExactlyValue(0.5) ||
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MO.getFPImm()->isExactlyValue(-0.5) ||
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MO.getFPImm()->isExactlyValue(1.0) ||
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MO.getFPImm()->isExactlyValue(-1.0) ||
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MO.getFPImm()->isExactlyValue(2.0) ||
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MO.getFPImm()->isExactlyValue(-2.0) ||
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MO.getFPImm()->isExactlyValue(4.0) ||
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MO.getFPImm()->isExactlyValue(-4.0);
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}
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return false;
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}
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bool SIInstrInfo::isLiteralConstant(const MachineOperand &MO) const {
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return (MO.isImm() || MO.isFPImm()) && !isInlineConstant(MO);
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}
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bool SIInstrInfo::verifyInstruction(const MachineInstr *MI,
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StringRef &ErrInfo) const {
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uint16_t Opcode = MI->getOpcode();
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int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0);
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int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1);
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int Src2Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2);
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// Verify VOP*
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if (isVOP1(Opcode) || isVOP2(Opcode) || isVOP3(Opcode) || isVOPC(Opcode)) {
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unsigned ConstantBusCount = 0;
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unsigned SGPRUsed = AMDGPU::NoRegister;
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for (int i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (MO.isReg() && MO.isUse() &&
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!TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
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// EXEC register uses the constant bus.
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if (!MO.isImplicit() && MO.getReg() == AMDGPU::EXEC)
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++ConstantBusCount;
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// SGPRs use the constant bus
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if (MO.getReg() == AMDGPU::M0 || MO.getReg() == AMDGPU::VCC ||
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(!MO.isImplicit() &&
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(AMDGPU::SGPR_32RegClass.contains(MO.getReg()) ||
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AMDGPU::SGPR_64RegClass.contains(MO.getReg())))) {
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if (SGPRUsed != MO.getReg()) {
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++ConstantBusCount;
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SGPRUsed = MO.getReg();
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}
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}
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}
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// Literal constants use the constant bus.
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if (isLiteralConstant(MO))
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++ConstantBusCount;
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}
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if (ConstantBusCount > 1) {
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ErrInfo = "VOP* instruction uses the constant bus more than once";
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return false;
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}
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}
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// Verify SRC1 for VOP2 and VOPC
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if (Src1Idx != -1 && (isVOP2(Opcode) || isVOPC(Opcode))) {
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const MachineOperand &Src1 = MI->getOperand(Src1Idx);
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if (Src1.isImm() || Src1.isFPImm()) {
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ErrInfo = "VOP[2C] src1 cannot be an immediate.";
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return false;
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}
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}
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// Verify VOP3
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if (isVOP3(Opcode)) {
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if (Src0Idx != -1 && isLiteralConstant(MI->getOperand(Src0Idx))) {
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ErrInfo = "VOP3 src0 cannot be a literal constant.";
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return false;
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}
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if (Src1Idx != -1 && isLiteralConstant(MI->getOperand(Src1Idx))) {
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ErrInfo = "VOP3 src1 cannot be a literal constant.";
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return false;
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}
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if (Src2Idx != -1 && isLiteralConstant(MI->getOperand(Src2Idx))) {
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ErrInfo = "VOP3 src2 cannot be a literal constant.";
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return false;
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}
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}
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return true;
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}
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unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) {
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switch (MI.getOpcode()) {
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default: return AMDGPU::INSTRUCTION_LIST_END;
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case AMDGPU::REG_SEQUENCE: return AMDGPU::REG_SEQUENCE;
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case AMDGPU::COPY: return AMDGPU::COPY;
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case AMDGPU::PHI: return AMDGPU::PHI;
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case AMDGPU::S_ASHR_I32: return AMDGPU::V_ASHR_I32_e32;
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case AMDGPU::S_ASHR_I64: return AMDGPU::V_ASHR_I64;
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case AMDGPU::S_LSHL_B32: return AMDGPU::V_LSHL_B32_e32;
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case AMDGPU::S_LSHL_B64: return AMDGPU::V_LSHL_B64;
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case AMDGPU::S_LSHR_B32: return AMDGPU::V_LSHR_B32_e32;
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case AMDGPU::S_LSHR_B64: return AMDGPU::V_LSHR_B64;
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}
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}
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bool SIInstrInfo::isSALUOpSupportedOnVALU(const MachineInstr &MI) const {
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return getVALUOp(MI) != AMDGPU::INSTRUCTION_LIST_END;
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}
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const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI,
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unsigned OpNo) const {
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const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
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const MCInstrDesc &Desc = get(MI.getOpcode());
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if (MI.isVariadic() || OpNo >= Desc.getNumOperands() ||
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Desc.OpInfo[OpNo].RegClass == -1)
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return MRI.getRegClass(MI.getOperand(OpNo).getReg());
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unsigned RCID = Desc.OpInfo[OpNo].RegClass;
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return RI.getRegClass(RCID);
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}
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bool SIInstrInfo::canReadVGPR(const MachineInstr &MI, unsigned OpNo) const {
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switch (MI.getOpcode()) {
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case AMDGPU::COPY:
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case AMDGPU::REG_SEQUENCE:
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return RI.hasVGPRs(getOpRegClass(MI, 0));
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default:
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return RI.hasVGPRs(getOpRegClass(MI, OpNo));
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}
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}
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void SIInstrInfo::legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const {
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MachineBasicBlock::iterator I = MI;
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MachineOperand &MO = MI->getOperand(OpIdx);
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MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
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unsigned RCID = get(MI->getOpcode()).OpInfo[OpIdx].RegClass;
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const TargetRegisterClass *RC = RI.getRegClass(RCID);
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unsigned Opcode = AMDGPU::V_MOV_B32_e32;
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if (MO.isReg()) {
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Opcode = AMDGPU::COPY;
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} else if (RI.isSGPRClass(RC)) {
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Opcode = AMDGPU::S_MOV_B32;
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}
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unsigned Reg = MRI.createVirtualRegister(RI.getRegClass(RCID));
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BuildMI(*MI->getParent(), I, MI->getParent()->findDebugLoc(I), get(Opcode),
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Reg).addOperand(MO);
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MO.ChangeToRegister(Reg, false);
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}
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void SIInstrInfo::legalizeOperands(MachineInstr *MI) const {
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MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
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int Src0Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
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AMDGPU::OpName::src0);
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int Src1Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
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AMDGPU::OpName::src1);
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int Src2Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
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AMDGPU::OpName::src2);
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// Legalize VOP2
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if (isVOP2(MI->getOpcode()) && Src1Idx != -1) {
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MachineOperand &Src1 = MI->getOperand(Src1Idx);
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// Legalize VOP2 instructions where src1 is not a VGPR. An SGPR input must
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// be the first operand, and there can only be one.
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if (Src1.isImm() || Src1.isFPImm() ||
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(Src1.isReg() && RI.isSGPRClass(MRI.getRegClass(Src1.getReg())))) {
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if (MI->isCommutable()) {
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if (commuteInstruction(MI))
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return;
|
|
}
|
|
legalizeOpWithMove(MI, Src1Idx);
|
|
}
|
|
}
|
|
|
|
// Legalize VOP3
|
|
if (isVOP3(MI->getOpcode())) {
|
|
int VOP3Idx[3] = {Src0Idx, Src1Idx, Src2Idx};
|
|
unsigned SGPRReg = AMDGPU::NoRegister;
|
|
for (unsigned i = 0; i < 3; ++i) {
|
|
int Idx = VOP3Idx[i];
|
|
if (Idx == -1)
|
|
continue;
|
|
MachineOperand &MO = MI->getOperand(Idx);
|
|
|
|
if (MO.isReg()) {
|
|
if (!RI.isSGPRClass(MRI.getRegClass(MO.getReg())))
|
|
continue; // VGPRs are legal
|
|
|
|
if (SGPRReg == AMDGPU::NoRegister || SGPRReg == MO.getReg()) {
|
|
SGPRReg = MO.getReg();
|
|
// We can use one SGPR in each VOP3 instruction.
|
|
continue;
|
|
}
|
|
} else if (!isLiteralConstant(MO)) {
|
|
// If it is not a register and not a literal constant, then it must be
|
|
// an inline constant which is always legal.
|
|
continue;
|
|
}
|
|
// If we make it this far, then the operand is not legal and we must
|
|
// legalize it.
|
|
legalizeOpWithMove(MI, Idx);
|
|
}
|
|
}
|
|
|
|
// Legalize REG_SEQUENCE
|
|
// The register class of the operands much be the same type as the register
|
|
// class of the output.
|
|
if (MI->getOpcode() == AMDGPU::REG_SEQUENCE) {
|
|
const TargetRegisterClass *RC = NULL, *SRC = NULL, *VRC = NULL;
|
|
for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
|
|
if (!MI->getOperand(i).isReg() ||
|
|
!TargetRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg()))
|
|
continue;
|
|
const TargetRegisterClass *OpRC =
|
|
MRI.getRegClass(MI->getOperand(i).getReg());
|
|
if (RI.hasVGPRs(OpRC)) {
|
|
VRC = OpRC;
|
|
} else {
|
|
SRC = OpRC;
|
|
}
|
|
}
|
|
|
|
// If any of the operands are VGPR registers, then they all most be
|
|
// otherwise we will create illegal VGPR->SGPR copies when legalizing
|
|
// them.
|
|
if (VRC || !RI.isSGPRClass(getOpRegClass(*MI, 0))) {
|
|
if (!VRC) {
|
|
assert(SRC);
|
|
VRC = RI.getEquivalentVGPRClass(SRC);
|
|
}
|
|
RC = VRC;
|
|
} else {
|
|
RC = SRC;
|
|
}
|
|
|
|
// Update all the operands so they have the same type.
|
|
for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
|
|
if (!MI->getOperand(i).isReg() ||
|
|
!TargetRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg()))
|
|
continue;
|
|
unsigned DstReg = MRI.createVirtualRegister(RC);
|
|
BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
|
|
get(AMDGPU::COPY), DstReg)
|
|
.addOperand(MI->getOperand(i));
|
|
MI->getOperand(i).setReg(DstReg);
|
|
}
|
|
}
|
|
}
|
|
|
|
void SIInstrInfo::moveToVALU(MachineInstr &TopInst) const {
|
|
SmallVector<MachineInstr *, 128> Worklist;
|
|
Worklist.push_back(&TopInst);
|
|
|
|
while (!Worklist.empty()) {
|
|
MachineInstr *Inst = Worklist.pop_back_val();
|
|
unsigned NewOpcode = getVALUOp(*Inst);
|
|
if (NewOpcode == AMDGPU::INSTRUCTION_LIST_END)
|
|
continue;
|
|
|
|
MachineRegisterInfo &MRI = Inst->getParent()->getParent()->getRegInfo();
|
|
|
|
// Use the new VALU Opcode.
|
|
const MCInstrDesc &NewDesc = get(NewOpcode);
|
|
Inst->setDesc(NewDesc);
|
|
|
|
// Add the implict and explicit register definitions.
|
|
if (NewDesc.ImplicitUses) {
|
|
for (unsigned i = 0; NewDesc.ImplicitUses[i]; ++i) {
|
|
Inst->addOperand(MachineOperand::CreateReg(NewDesc.ImplicitUses[i],
|
|
false, true));
|
|
}
|
|
}
|
|
|
|
if (NewDesc.ImplicitDefs) {
|
|
for (unsigned i = 0; NewDesc.ImplicitDefs[i]; ++i) {
|
|
Inst->addOperand(MachineOperand::CreateReg(NewDesc.ImplicitDefs[i],
|
|
true, true));
|
|
}
|
|
}
|
|
|
|
legalizeOperands(Inst);
|
|
|
|
// Update the destination register class.
|
|
const TargetRegisterClass *NewDstRC = getOpRegClass(*Inst, 0);
|
|
|
|
switch (Inst->getOpcode()) {
|
|
// For target instructions, getOpRegClass just returns the virtual
|
|
// register class associated with the operand, so we need to find an
|
|
// equivalent VGPR register class in order to move the instruction to the
|
|
// VALU.
|
|
case AMDGPU::COPY:
|
|
case AMDGPU::PHI:
|
|
case AMDGPU::REG_SEQUENCE:
|
|
if (RI.hasVGPRs(NewDstRC))
|
|
continue;
|
|
NewDstRC = RI.getEquivalentVGPRClass(NewDstRC);
|
|
if (!NewDstRC)
|
|
continue;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
unsigned DstReg = Inst->getOperand(0).getReg();
|
|
unsigned NewDstReg = MRI.createVirtualRegister(NewDstRC);
|
|
MRI.replaceRegWith(DstReg, NewDstReg);
|
|
|
|
for (MachineRegisterInfo::use_iterator I = MRI.use_begin(NewDstReg),
|
|
E = MRI.use_end(); I != E; ++I) {
|
|
MachineInstr &UseMI = *I;
|
|
if (!canReadVGPR(UseMI, I.getOperandNo())) {
|
|
Worklist.push_back(&UseMI);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Indirect addressing callbacks
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
unsigned SIInstrInfo::calculateIndirectAddress(unsigned RegIndex,
|
|
unsigned Channel) const {
|
|
assert(Channel == 0);
|
|
return RegIndex;
|
|
}
|
|
|
|
const TargetRegisterClass *SIInstrInfo::getIndirectAddrRegClass() const {
|
|
return &AMDGPU::VReg_32RegClass;
|
|
}
|
|
|
|
MachineInstrBuilder SIInstrInfo::buildIndirectWrite(
|
|
MachineBasicBlock *MBB,
|
|
MachineBasicBlock::iterator I,
|
|
unsigned ValueReg,
|
|
unsigned Address, unsigned OffsetReg) const {
|
|
const DebugLoc &DL = MBB->findDebugLoc(I);
|
|
unsigned IndirectBaseReg = AMDGPU::VReg_32RegClass.getRegister(
|
|
getIndirectIndexBegin(*MBB->getParent()));
|
|
|
|
return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_DST_V1))
|
|
.addReg(IndirectBaseReg, RegState::Define)
|
|
.addOperand(I->getOperand(0))
|
|
.addReg(IndirectBaseReg)
|
|
.addReg(OffsetReg)
|
|
.addImm(0)
|
|
.addReg(ValueReg);
|
|
}
|
|
|
|
MachineInstrBuilder SIInstrInfo::buildIndirectRead(
|
|
MachineBasicBlock *MBB,
|
|
MachineBasicBlock::iterator I,
|
|
unsigned ValueReg,
|
|
unsigned Address, unsigned OffsetReg) const {
|
|
const DebugLoc &DL = MBB->findDebugLoc(I);
|
|
unsigned IndirectBaseReg = AMDGPU::VReg_32RegClass.getRegister(
|
|
getIndirectIndexBegin(*MBB->getParent()));
|
|
|
|
return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_SRC))
|
|
.addOperand(I->getOperand(0))
|
|
.addOperand(I->getOperand(1))
|
|
.addReg(IndirectBaseReg)
|
|
.addReg(OffsetReg)
|
|
.addImm(0);
|
|
|
|
}
|
|
|
|
void SIInstrInfo::reserveIndirectRegisters(BitVector &Reserved,
|
|
const MachineFunction &MF) const {
|
|
int End = getIndirectIndexEnd(MF);
|
|
int Begin = getIndirectIndexBegin(MF);
|
|
|
|
if (End == -1)
|
|
return;
|
|
|
|
|
|
for (int Index = Begin; Index <= End; ++Index)
|
|
Reserved.set(AMDGPU::VReg_32RegClass.getRegister(Index));
|
|
|
|
for (int Index = std::max(0, Begin - 1); Index <= End; ++Index)
|
|
Reserved.set(AMDGPU::VReg_64RegClass.getRegister(Index));
|
|
|
|
for (int Index = std::max(0, Begin - 2); Index <= End; ++Index)
|
|
Reserved.set(AMDGPU::VReg_96RegClass.getRegister(Index));
|
|
|
|
for (int Index = std::max(0, Begin - 3); Index <= End; ++Index)
|
|
Reserved.set(AMDGPU::VReg_128RegClass.getRegister(Index));
|
|
|
|
for (int Index = std::max(0, Begin - 7); Index <= End; ++Index)
|
|
Reserved.set(AMDGPU::VReg_256RegClass.getRegister(Index));
|
|
|
|
for (int Index = std::max(0, Begin - 15); Index <= End; ++Index)
|
|
Reserved.set(AMDGPU::VReg_512RegClass.getRegister(Index));
|
|
}
|