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e7c1416263
ARM register class allocation order functions to take advantage of that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112841 91177308-0d34-0410-b5e6-96231b3b80d8
42 lines
1.6 KiB
LLVM
42 lines
1.6 KiB
LLVM
; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 -relocation-model=pic | FileCheck %s
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; rdar://7387640
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; This now reduces to a single induction variable.
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; TODO: It still gets a GPR shuffle at the end of the loop
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; This is because something in instruction selection has decided
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; that comparing the pre-incremented value with zero is better
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; than comparing the post-incremented value with -4.
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@G = external global i32 ; <i32*> [#uses=2]
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@array = external global i32* ; <i32**> [#uses=1]
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define void @t() nounwind optsize {
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; CHECK: t:
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; CHECK: mov.w r2, #1000
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entry:
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%.pre = load i32* @G, align 4 ; <i32> [#uses=1]
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br label %bb
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bb: ; preds = %bb, %entry
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; CHECK: LBB0_1:
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; CHECK: cmp r2, #0
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; CHECK: sub{{(.w)?}} [[REGISTER:(r[0-9]+)|(lr)]], r2, #1
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; CHECK: mov r2, [[REGISTER]]
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%0 = phi i32 [ %.pre, %entry ], [ %3, %bb ] ; <i32> [#uses=1]
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%indvar = phi i32 [ 0, %entry ], [ %indvar.next, %bb ] ; <i32> [#uses=2]
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%tmp5 = sub i32 1000, %indvar ; <i32> [#uses=1]
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%1 = load i32** @array, align 4 ; <i32*> [#uses=1]
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%scevgep = getelementptr i32* %1, i32 %tmp5 ; <i32*> [#uses=1]
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%2 = load i32* %scevgep, align 4 ; <i32> [#uses=1]
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%3 = add nsw i32 %2, %0 ; <i32> [#uses=2]
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store i32 %3, i32* @G, align 4
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%indvar.next = add i32 %indvar, 1 ; <i32> [#uses=2]
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%exitcond = icmp eq i32 %indvar.next, 1001 ; <i1> [#uses=1]
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br i1 %exitcond, label %return, label %bb
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return: ; preds = %bb
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ret void
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}
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