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c96096cc0f
Summary:
This required me to implement the disassembler for MIPS64r6 since the encodings
are ambiguous with other instructions. This in turn revealed a few
assembly/disassembly bugs which I have fixed.
* da[ht]i only take two operands according to the spec, not three.
* DecodeBranchTarget2[16] correctly handles wider immediates than simm16
* Also made non-functional change to DecodeBranchTarget and
DecodeBranchTargetMM to keep implementation style consistent between
them.
* Difficult encodings are handled by a custom decode method on the most
general encoding in the group. This method will convert the MCInst to a
different opcode if necessary.
DecodeBranchTarget is not currently the inverse of getBranchTargetOpValue
so disassembling some branch instructions emit incorrect output. This seems
to affect branches with delay slots on all MIPS ISA's. I've left this bug
for now and temporarily removed the check for the immediate on
bc[12]eqz/bc[12]nez in the MIPS32r6/MIPS64r6 tests.
jialc and jic crash the disassembler for some reason. I've left these
instructions commented out for the moment.
Depends on D3760
Reviewers: jkolek, zoran.jovanovic, vmedic
Reviewed By: vmedic
Differential Revision: http://reviews.llvm.org/D3761
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209415 91177308-0d34-0410-b5e6-96231b3b80d8
387 lines
9.3 KiB
TableGen
387 lines
9.3 KiB
TableGen
//=- Mips32r6InstrFormats.td - Mips32r6 Instruction Formats -*- tablegen -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes Mips32r6 instruction formats.
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//
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//===----------------------------------------------------------------------===//
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class MipsR6Inst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther>,
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PredicateControl {
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let DecoderNamespace = "Mips32r6_64r6";
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let EncodingPredicates = [HasStdEnc];
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}
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//===----------------------------------------------------------------------===//
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//
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// Field Values
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//
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//===----------------------------------------------------------------------===//
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class OPGROUP<bits<6> Val> {
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bits<6> Value = Val;
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}
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def OPGROUP_COP1 : OPGROUP<0b010001>;
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def OPGROUP_COP2 : OPGROUP<0b010010>;
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def OPGROUP_ADDI : OPGROUP<0b001000>;
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def OPGROUP_AUI : OPGROUP<0b001111>;
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def OPGROUP_BLEZ : OPGROUP<0b000110>;
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def OPGROUP_BGTZ : OPGROUP<0b000111>;
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def OPGROUP_BLEZL : OPGROUP<0b010110>;
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def OPGROUP_BGTZL : OPGROUP<0b010111>;
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def OPGROUP_DADDI : OPGROUP<0b011000>;
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def OPGROUP_DAUI : OPGROUP<0b011101>;
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def OPGROUP_PCREL : OPGROUP<0b111011>;
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def OPGROUP_REGIMM : OPGROUP<0b000001>;
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def OPGROUP_SPECIAL : OPGROUP<0b000000>;
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def OPGROUP_SPECIAL3 : OPGROUP<0b011111>;
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class OPCODE2<bits<2> Val> {
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bits<2> Value = Val;
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}
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def OPCODE2_ADDIUPC : OPCODE2<0b00>;
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def OPCODE2_LWPC : OPCODE2<0b01>;
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def OPCODE2_LWUPC : OPCODE2<0b10>;
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class OPCODE5<bits<5> Val> {
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bits<5> Value = Val;
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}
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def OPCODE5_ALUIPC : OPCODE5<0b11111>;
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def OPCODE5_AUIPC : OPCODE5<0b11110>;
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def OPCODE5_DAHI : OPCODE5<0b00110>;
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def OPCODE5_DATI : OPCODE5<0b11110>;
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def OPCODE5_BC1EQZ : OPCODE5<0b01001>;
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def OPCODE5_BC1NEZ : OPCODE5<0b01101>;
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def OPCODE5_BC2EQZ : OPCODE5<0b01001>;
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def OPCODE5_BC2NEZ : OPCODE5<0b01101>;
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class OPCODE6<bits<6> Val> {
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bits<6> Value = Val;
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}
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def OPCODE6_ALIGN : OPCODE6<0b100000>;
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def OPCODE6_DALIGN : OPCODE6<0b100100>;
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def OPCODE6_BITSWAP : OPCODE6<0b100000>;
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def OPCODE6_DBITSWAP : OPCODE6<0b100100>;
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class FIELD_FMT<bits<5> Val> {
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bits<5> Value = Val;
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}
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def FIELD_FMT_S : FIELD_FMT<0b10000>;
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def FIELD_FMT_D : FIELD_FMT<0b10001>;
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class FIELD_CMP_COND<bits<5> Val> {
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bits<5> Value = Val;
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}
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def FIELD_CMP_COND_F : FIELD_CMP_COND<0b00000>;
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def FIELD_CMP_COND_UN : FIELD_CMP_COND<0b00001>;
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def FIELD_CMP_COND_EQ : FIELD_CMP_COND<0b00010>;
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def FIELD_CMP_COND_UEQ : FIELD_CMP_COND<0b00011>;
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def FIELD_CMP_COND_OLT : FIELD_CMP_COND<0b00100>;
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def FIELD_CMP_COND_ULT : FIELD_CMP_COND<0b00101>;
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def FIELD_CMP_COND_OLE : FIELD_CMP_COND<0b00110>;
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def FIELD_CMP_COND_ULE : FIELD_CMP_COND<0b00111>;
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def FIELD_CMP_COND_SF : FIELD_CMP_COND<0b01000>;
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def FIELD_CMP_COND_NGLE : FIELD_CMP_COND<0b01001>;
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def FIELD_CMP_COND_SEQ : FIELD_CMP_COND<0b01010>;
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def FIELD_CMP_COND_NGL : FIELD_CMP_COND<0b01011>;
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def FIELD_CMP_COND_LT : FIELD_CMP_COND<0b01100>;
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def FIELD_CMP_COND_NGE : FIELD_CMP_COND<0b01101>;
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def FIELD_CMP_COND_LE : FIELD_CMP_COND<0b01110>;
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def FIELD_CMP_COND_NGT : FIELD_CMP_COND<0b01111>;
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class FIELD_CMP_FORMAT<bits<5> Val> {
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bits<5> Value = Val;
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}
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def FIELD_CMP_FORMAT_S : FIELD_CMP_FORMAT<0b10100>;
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def FIELD_CMP_FORMAT_D : FIELD_CMP_FORMAT<0b10101>;
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//===----------------------------------------------------------------------===//
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//
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// Disambiguators
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//
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//===----------------------------------------------------------------------===//
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//
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// Some encodings are ambiguous except by comparing field values.
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class DecodeDisambiguates<string Name> {
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string DecoderMethod = !strconcat("Decode", Name);
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}
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class DecodeDisambiguatedBy<string Name> : DecodeDisambiguates<Name> {
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string DecoderNamespace = "Mips32r6_64r6_Ambiguous";
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}
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//===----------------------------------------------------------------------===//
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//
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// Encoding Formats
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//
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//===----------------------------------------------------------------------===//
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class AUI_FM : MipsR6Inst {
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bits<5> rs;
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bits<5> rt;
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bits<16> imm;
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bits<32> Inst;
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let Inst{31-26} = OPGROUP_AUI.Value;
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let Inst{25-21} = rs;
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let Inst{20-16} = rt;
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let Inst{15-0} = imm;
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}
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class DAUI_FM : AUI_FM {
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let Inst{31-26} = OPGROUP_DAUI.Value;
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}
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class COP1_2R_FM<bits<6> funct, FIELD_FMT Format> : MipsR6Inst {
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bits<5> fs;
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bits<5> fd;
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bits<32> Inst;
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let Inst{31-26} = OPGROUP_COP1.Value;
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let Inst{25-21} = Format.Value;
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let Inst{20-16} = 0b00000;
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let Inst{15-11} = fs;
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let Inst{10-6} = fd;
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let Inst{5-0} = funct;
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}
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class COP1_3R_FM<bits<6> funct, FIELD_FMT Format> : MipsR6Inst {
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bits<5> ft;
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bits<5> fs;
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bits<5> fd;
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bits<32> Inst;
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let Inst{31-26} = OPGROUP_COP1.Value;
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let Inst{25-21} = Format.Value;
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let Inst{20-16} = ft;
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let Inst{15-11} = fs;
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let Inst{10-6} = fd;
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let Inst{5-0} = funct;
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}
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class COP1_BCCZ_FM<OPCODE5 Operation> : MipsR6Inst {
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bits<5> ft;
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bits<16> offset;
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bits<32> Inst;
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let Inst{31-26} = OPGROUP_COP1.Value;
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let Inst{25-21} = Operation.Value;
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let Inst{20-16} = ft;
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let Inst{15-0} = offset;
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}
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class COP2_BCCZ_FM<OPCODE5 Operation> : MipsR6Inst {
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bits<5> ct;
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bits<16> offset;
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bits<32> Inst;
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let Inst{31-26} = OPGROUP_COP2.Value;
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let Inst{25-21} = Operation.Value;
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let Inst{20-16} = ct;
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let Inst{15-0} = offset;
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}
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class PCREL16_FM<OPCODE5 Operation> : MipsR6Inst {
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bits<5> rs;
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bits<16> imm;
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bits<32> Inst;
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let Inst{31-26} = OPGROUP_PCREL.Value;
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let Inst{25-21} = rs;
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let Inst{20-16} = Operation.Value;
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let Inst{15-0} = imm;
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}
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class PCREL19_FM<OPCODE2 Operation> : MipsR6Inst {
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bits<5> rs;
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bits<19> imm;
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bits<32> Inst;
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let Inst{31-26} = OPGROUP_PCREL.Value;
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let Inst{25-21} = rs;
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let Inst{20-19} = Operation.Value;
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let Inst{18-0} = imm;
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}
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class SPECIAL3_2R_FM<OPCODE6 Operation> : MipsR6Inst {
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bits<5> rd;
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bits<5> rt;
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bits<32> Inst;
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let Inst{31-26} = OPGROUP_SPECIAL3.Value;
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let Inst{25-21} = 0b00000;
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let Inst{20-16} = rt;
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let Inst{15-11} = rd;
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let Inst{10-6} = 0b00000;
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let Inst{5-0} = Operation.Value;
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}
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class SPECIAL_3R_FM<bits<5> mulop, bits<6> funct> : MipsR6Inst {
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bits<5> rd;
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bits<5> rs;
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bits<5> rt;
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bits<32> Inst;
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let Inst{31-26} = OPGROUP_SPECIAL.Value;
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let Inst{25-21} = rs;
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let Inst{20-16} = rt;
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let Inst{15-11} = rd;
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let Inst{10-6} = mulop;
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let Inst{5-0} = funct;
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}
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// This class is ambiguous with other branches:
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// BEQC/BNEC require that rs > rt
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class CMP_BRANCH_2R_OFF16_FM<OPGROUP funct> : MipsR6Inst {
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bits<5> rs;
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bits<5> rt;
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bits<16> offset;
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bits<32> Inst;
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let Inst{31-26} = funct.Value;
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let Inst{25-21} = rs;
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let Inst{20-16} = rt;
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let Inst{15-0} = offset;
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}
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// This class is ambiguous with other branches:
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// BLEZC/BGEZC/BEQZALC/BNEZALC/BGTZALC require that rs == 0 && rt != 0
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// The '1R_RT' in the name means 1 register in the rt field.
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class CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP funct> : MipsR6Inst {
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bits<5> rt;
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bits<16> offset;
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bits<32> Inst;
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let Inst{31-26} = funct.Value;
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let Inst{25-21} = 0b00000;
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let Inst{20-16} = rt;
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let Inst{15-0} = offset;
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}
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// This class is ambiguous with other branches:
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// BLTZC/BGTZC/BLTZALC/BGEZALC require that rs == rt && rt != 0
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// The '1R_BOTH' in the name means 1 register in both the rs and rt fields.
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class CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP funct> : MipsR6Inst {
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bits<5> rt;
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bits<16> offset;
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bits<32> Inst;
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let Inst{31-26} = funct.Value;
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let Inst{25-21} = rt;
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let Inst{20-16} = rt;
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let Inst{15-0} = offset;
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}
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class CMP_BRANCH_OFF21_FM<bits<6> funct> : MipsR6Inst {
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bits<5> rs; // rs != 0
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bits<21> offset;
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bits<32> Inst;
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let Inst{31-26} = funct;
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let Inst{25-21} = rs;
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let Inst{20-0} = offset;
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}
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class JMP_IDX_COMPACT_FM<bits<6> funct> : MipsR6Inst {
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bits<5> rt;
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bits<16> offset;
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bits<32> Inst;
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let Inst{31-26} = funct;
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let Inst{25-21} = 0b000000;
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let Inst{20-16} = rt;
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let Inst{15-0} = offset;
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}
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class BRANCH_OFF26_FM<bits<6> funct> : MipsR6Inst {
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bits<32> Inst;
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bits<26> offset;
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let Inst{31-26} = funct;
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let Inst{25-0} = offset;
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}
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class SPECIAL3_ALIGN_FM<OPCODE6 Operation> : MipsR6Inst {
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bits<5> rd;
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bits<5> rs;
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bits<5> rt;
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bits<2> bp;
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bits<32> Inst;
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let Inst{31-26} = OPGROUP_SPECIAL3.Value;
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let Inst{25-21} = rs;
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let Inst{20-16} = rt;
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let Inst{15-11} = rd;
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let Inst{10-8} = 0b010;
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let Inst{7-6} = bp;
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let Inst{5-0} = Operation.Value;
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}
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class SPECIAL3_DALIGN_FM<OPCODE6 Operation> : MipsR6Inst {
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bits<5> rd;
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bits<5> rs;
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bits<5> rt;
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bits<3> bp;
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bits<32> Inst;
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let Inst{31-26} = OPGROUP_SPECIAL3.Value;
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let Inst{25-21} = rs;
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let Inst{20-16} = rt;
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let Inst{15-11} = rd;
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let Inst{10-9} = 0b01;
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let Inst{8-6} = bp;
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let Inst{5-0} = Operation.Value;
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}
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class REGIMM_FM<OPCODE5 Operation> : MipsR6Inst {
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bits<5> rs;
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bits<16> imm;
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bits<32> Inst;
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let Inst{31-26} = OPGROUP_REGIMM.Value;
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let Inst{25-21} = rs;
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let Inst{20-16} = Operation.Value;
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let Inst{15-0} = imm;
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}
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class COP1_CMP_CONDN_FM<FIELD_CMP_FORMAT Format,
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FIELD_CMP_COND Cond> : MipsR6Inst {
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bits<5> fd;
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bits<5> fs;
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bits<5> ft;
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bits<32> Inst;
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let Inst{31-26} = OPGROUP_COP1.Value;
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let Inst{25-21} = Format.Value;
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let Inst{20-16} = ft;
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let Inst{15-11} = fs;
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let Inst{10-6} = fd;
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let Inst{5} = 0;
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let Inst{4-0} = Cond.Value;
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}
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